initial commit. Fork von magic994
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commit
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EESchema-DOCLIB Version 2.0
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||||
#
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||||
#End Doc Library
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||||
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@ -0,0 +1,265 @@
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|||
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||||
(rules PCB DLP
|
||||
(snap_angle
|
||||
fortyfive_degree
|
||||
)
|
||||
(autoroute_settings
|
||||
(fanout off)
|
||||
(autoroute on)
|
||||
(postroute on)
|
||||
(vias on)
|
||||
(via_costs 50)
|
||||
(plane_via_costs 5)
|
||||
(start_ripup_costs 100)
|
||||
(start_pass_no 33527)
|
||||
(layer_rule F.Cu
|
||||
(active on)
|
||||
(preferred_direction horizontal)
|
||||
(preferred_direction_trace_costs 1.0)
|
||||
(against_preferred_direction_trace_costs 2.5)
|
||||
)
|
||||
(layer_rule B.Cu
|
||||
(active on)
|
||||
(preferred_direction vertical)
|
||||
(preferred_direction_trace_costs 1.0)
|
||||
(against_preferred_direction_trace_costs 1.7)
|
||||
)
|
||||
)
|
||||
(rule
|
||||
(width 600.0)
|
||||
(clear 250.2)
|
||||
(clear 300.0 (type smd_to_turn_gap))
|
||||
(clear 300.2 (type default_Analogsignale))
|
||||
(clear 750.2 (type default_GND))
|
||||
(clear 500.2 (type default_Spannungen))
|
||||
(clear 62.6 (type smd_smd))
|
||||
(clear 300.2 (type smd_Analogsignale))
|
||||
(clear 750.2 (type smd_GND))
|
||||
(clear 500.2 (type smd_Spannungen))
|
||||
(clear 300.2 (type "kicad_default"_Analogsignale))
|
||||
(clear 750.2 (type "kicad_default"_GND))
|
||||
(clear 500.2 (type "kicad_default"_Spannungen))
|
||||
(clear 100.2 (type Adressen_Adressen))
|
||||
(clear 300.2 (type Adressen_Analogsignale))
|
||||
(clear 750.2 (type Adressen_GND))
|
||||
(clear 500.2 (type Adressen_Spannungen))
|
||||
(clear 300.2 (type Analogsignale_Analogsignale))
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||||
(clear 300.2 (type Analogsignale_Daten))
|
||||
(clear 750.2 (type Analogsignale_GND))
|
||||
(clear 500.2 (type Analogsignale_Spannungen))
|
||||
(clear 300.2 (type Analogsignale_Steuersignale))
|
||||
(clear 100.2 (type Daten_Daten))
|
||||
(clear 750.2 (type Daten_GND))
|
||||
(clear 500.2 (type Daten_Spannungen))
|
||||
(clear 750.2 (type GND_GND))
|
||||
(clear 750.2 (type GND_Spannungen))
|
||||
(clear 750.2 (type GND_Steuersignale))
|
||||
(clear 500.2 (type Spannungen_Spannungen))
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||||
(clear 500.2 (type Spannungen_Steuersignale))
|
||||
(clear 200.2 (type Steuersignale_Steuersignale))
|
||||
)
|
||||
(padstack "Via[0-1]_800:400_um"
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||||
(shape
|
||||
(circle F.Cu 800.0 0.0 0.0)
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||||
)
|
||||
(shape
|
||||
(circle B.Cu 800.0 0.0 0.0)
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||||
)
|
||||
(attach off)
|
||||
)
|
||||
(padstack "Via[0-1]_1200:600_um"
|
||||
(shape
|
||||
(circle F.Cu 1200.0 0.0 0.0)
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||||
)
|
||||
(shape
|
||||
(circle B.Cu 1200.0 0.0 0.0)
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||||
)
|
||||
(attach off)
|
||||
)
|
||||
(via
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||||
"Via[0-1]_800:400_um" "Via[0-1]_800:400_um" default
|
||||
)
|
||||
(via
|
||||
"Via[0-1]_1200:600_um" "Via[0-1]_1200:600_um" default
|
||||
)
|
||||
(via
|
||||
"Via[0-1]_800:400_um-kicad_default" "Via[0-1]_800:400_um" "kicad_default"
|
||||
)
|
||||
(via
|
||||
"Via[0-1]_1200:600_um-kicad_default" "Via[0-1]_1200:600_um" "kicad_default"
|
||||
)
|
||||
(via
|
||||
"Via[0-1]_800:400_um-Adressen" "Via[0-1]_800:400_um" Adressen
|
||||
)
|
||||
(via
|
||||
"Via[0-1]_1200:600_um-Adressen" "Via[0-1]_1200:600_um" Adressen
|
||||
)
|
||||
(via
|
||||
"Via[0-1]_800:400_um-Analogsignale" "Via[0-1]_800:400_um" Analogsignale
|
||||
)
|
||||
(via
|
||||
"Via[0-1]_1200:600_um-Analogsignale" "Via[0-1]_1200:600_um" Analogsignale
|
||||
)
|
||||
(via
|
||||
"Via[0-1]_800:400_um-Daten" "Via[0-1]_800:400_um" Daten
|
||||
)
|
||||
(via
|
||||
"Via[0-1]_1200:600_um-Daten" "Via[0-1]_1200:600_um" Daten
|
||||
)
|
||||
(via
|
||||
"Via[0-1]_800:400_um-GND" "Via[0-1]_800:400_um" GND
|
||||
)
|
||||
(via
|
||||
"Via[0-1]_1200:600_um-GND" "Via[0-1]_1200:600_um" GND
|
||||
)
|
||||
(via
|
||||
"Via[0-1]_800:400_um-Spannungen" "Via[0-1]_800:400_um" Spannungen
|
||||
)
|
||||
(via
|
||||
"Via[0-1]_1200:600_um-Spannungen" "Via[0-1]_1200:600_um" Spannungen
|
||||
)
|
||||
(via
|
||||
"Via[0-1]_800:400_um-Steuersignale" "Via[0-1]_800:400_um" Steuersignale
|
||||
)
|
||||
(via
|
||||
"Via[0-1]_1200:600_um-Steuersignale" "Via[0-1]_1200:600_um" Steuersignale
|
||||
)
|
||||
(via_rule
|
||||
default "Via[0-1]_800:400_um"
|
||||
)
|
||||
(via_rule
|
||||
"kicad_default" "Via[0-1]_800:400_um-kicad_default"
|
||||
)
|
||||
(via_rule
|
||||
Adressen "Via[0-1]_800:400_um-Adressen"
|
||||
)
|
||||
(via_rule
|
||||
Analogsignale "Via[0-1]_800:400_um-Analogsignale"
|
||||
)
|
||||
(via_rule
|
||||
Daten "Via[0-1]_800:400_um-Daten"
|
||||
)
|
||||
(via_rule
|
||||
GND "Via[0-1]_800:400_um-GND"
|
||||
)
|
||||
(via_rule
|
||||
Spannungen "Via[0-1]_1200:600_um-Spannungen"
|
||||
)
|
||||
(via_rule
|
||||
Steuersignale "Via[0-1]_800:400_um-Steuersignale"
|
||||
)
|
||||
(class default
|
||||
(clearance_class default)
|
||||
(via_rule default)
|
||||
(rule
|
||||
(width 600.0)
|
||||
)
|
||||
(circuit
|
||||
(use_layer F.Cu B.Cu)
|
||||
)
|
||||
)
|
||||
(class "kicad_default"
|
||||
"Net-(D101-Pad12)" "Net-(C109-Pad2)" "Net-(C101-Pad2)" "Net-(C101-Pad1)" "Net-(D101-Pad2)" "Net-(D101-Pad8)" "Net-(C109-Pad1)" "Net-(D102-Pad2)"
|
||||
"Net-(C104-Pad2)" "Net-(D104-Pad19)" "Net-(D104-Pad28)" "Net-(D104-Pad25)" "Net-(D104-Pad5)" "Net-(D104-Pad24)" "Net-(D104-Pad4)" "Net-(D104-Pad23)"
|
||||
CS7 CS5 CS6 U3 U2 U1 U0 "Net-(C102-Pad1)"
|
||||
"Net-(U1-Pad6)" "Net-(U1-Pad3)" "Net-(U1-Pad2)" RxTxCB "Net-(D116-Pad20)" "X120A-A5" "Net-(C104-Pad1)" "Net-(C110-Pad2)"
|
||||
"Net-(C134-Pad2)" "X120A-B2" "X120A-A2" "Net-(C146-Pad1)" "Net-(C147-Pad2)" "Net-(C147-Pad1)" "X120A-A11" "Net-(C150-Pad1)"
|
||||
"Net-(D1-Pad1)" "Net-(D112-Pad8)" "Net-(D113-Pad8)" 110 "Net-(D117-Pad10)" "Net-(D122-Pad18)" "Net-(D122-Pad17)" "Net-(D122-Pad16)"
|
||||
"X160M-B1" "X160M-B2" "X160M-B3" "X160M-B4" "X130B-A2" "X120A-A7" "X130B-B2" "X120A-A8"
|
||||
"X130B-A1" "X120A-A9" "X130B-B1" "X120A-B6" "Net-(D122-Pad24)" "Net-(D122-Pad22)" "Net-(D122-Pad21)" "X160M-A9"
|
||||
"X160M-B12" "X160M-A10" "X160M-A11" "X160M-A12" "X160M-A13" "X160M-B10" "X160M-B11" "X160M-A1"
|
||||
"X160M-A8" "X160M-A2" "X160M-A3" "X160M-A4" "X160M-A5" "X160M-A6" "X160M-A7" "Net-(D125-Pad19)"
|
||||
"Net-(D125-Pad18)" "Net-(D125-Pad17)" "Net-(D125-Pad16)" "Net-(D125-Pad15)" "Net-(D125-Pad14)" "Net-(D125-Pad13)" "Net-(D125-Pad12)" "Net-(D125-Pad11)"
|
||||
"Net-(D125-Pad30)" "Net-(D125-Pad10)" "Net-(D125-Pad29)" "Net-(D125-Pad26)" "Net-(D125-Pad25)" "Net-(D125-Pad24)" "Net-(D125-Pad23)" "Net-(D125-Pad22)"
|
||||
"Net-(D126-Pad6)" "Net-(D126-Pad3)" "Net-(D126-Pad10)" "Net-(D126-Pad8)" "Net-(D129-Pad18)" "Net-(D129-Pad17)" "Net-(D129-Pad16)" "X130B-A10"
|
||||
"Net-(D129-Pad34)" "X130B-B10" "Net-(D129-Pad33)" "X130B-A11" "Net-(D129-Pad32)" "X130B-B11" "Net-(D129-Pad31)" "Net-(D129-Pad30)"
|
||||
"X130B-A12" "Net-(D129-Pad29)" "X130B-B12" "Net-(D129-Pad28)" "X130B-A13" "Net-(D129-Pad27)" "X130B-B13" "Net-(D129-Pad24)"
|
||||
"Net-(D129-Pad23)" "Net-(D129-Pad22)" "Net-(D129-Pad21)" "Net-(D130-Pad18)" "Net-(D130-Pad17)" "Net-(D130-Pad16)" "X120A-B3" "X120A-A13"
|
||||
"X120A-B4" "X120A-A12" "Net-(D130-Pad13)" "X120A-B7" "Net-(D130-Pad12)" "X120A-B11" "X120A-A10" "Net-(D130-Pad10)"
|
||||
"X120A-B10" "X120A-B12" "X120A-B9" "X120A-B13" "X120A-B8" "Net-(D130-Pad7)" "Net-(D130-Pad22)" "Net-(D130-Pad21)"
|
||||
"Net-(D131-Pad10)" "Net-(D131-Pad6)" "Net-(D131-Pad1)" "Net-(D131-Pad3)" 109 112 "Net-(N103-Pad4)" "X120A-B1"
|
||||
"X120A-B5" "RES_SW" "Net-(R117-Pad2)" "Net-(R135-Pad2)" "Net-(R136-Pad2)" "Net-(R137-Pad2)" "Net-(R137-Pad1)" "Net-(R140-Pad2)"
|
||||
"Net-(R141-Pad1)" "Net-(R143-Pad1)" "Net-(X120A1-Pad11)" "Net-(X120A1-Pad7)" "Net-(X120A1-Pad5)" "Net-(X130B1-Pad18)" "Net-(X130B1-Pad17)" "Net-(X130B1-Pad16)"
|
||||
"Net-(X130B1-Pad15)" "Net-(X130B1-Pad10)" "Net-(X130B1-Pad9)" "Net-(X130B1-Pad8)" "Net-(X130B1-Pad7)" "Net-(X130B1-Pad6)" "Net-(X130B1-Pad5)" "Net-(XMI1-Pad3)"
|
||||
"Net-(XMI1-Pad2)" "Net-(XMO1-Pad3)" "Net-(XMO1-Pad1)" "Net-(XMT1-Pad3)" "Net-(XMT1-Pad1)" "Net-(D122-Pad23)" "MIDI-Rx" "Net-(N104-Pad11)"
|
||||
"Net-(N104-Pad2)" "Net-(N104-Pad1)" CS0 CS1 CS2 CS3 JOE0 JCS0
|
||||
JOE1 JCS1 JOE2 JCS2 JOE3 JCS3 JCS8 JOE8
|
||||
CS8 "Net-(U2-Pad10)"
|
||||
(clearance_class "kicad_default")
|
||||
(via_rule kicad_default)
|
||||
(rule
|
||||
(width 600.0)
|
||||
)
|
||||
(circuit
|
||||
(use_layer F.Cu B.Cu)
|
||||
)
|
||||
)
|
||||
(class Adressen
|
||||
/A10 /A9 /A8 /A7 /A6 /A5 /A4 /A3
|
||||
/A1 /A0 /A13 /A12 /A2 /A11
|
||||
(clearance_class Adressen)
|
||||
(via_rule Adressen)
|
||||
(rule
|
||||
(width 350.0)
|
||||
)
|
||||
(circuit
|
||||
(use_layer F.Cu B.Cu)
|
||||
)
|
||||
)
|
||||
(class Analogsignale
|
||||
103 "Net-(N102-Pad8)" "Net-(N102-Pad3)" "Net-(N102-Pad5)" "Net-(N102-Pad1)"
|
||||
(clearance_class Analogsignale)
|
||||
(via_rule Analogsignale)
|
||||
(rule
|
||||
(width 800.0)
|
||||
)
|
||||
(circuit
|
||||
(use_layer F.Cu B.Cu)
|
||||
)
|
||||
)
|
||||
(class Daten
|
||||
/D1 /D0 /D7 /D2 /D6 /D5 /D3 /D4
|
||||
(clearance_class Daten)
|
||||
(via_rule Daten)
|
||||
(rule
|
||||
(width 350.0)
|
||||
)
|
||||
(circuit
|
||||
(use_layer F.Cu B.Cu)
|
||||
)
|
||||
)
|
||||
(class GND
|
||||
105
|
||||
(clearance_class GND)
|
||||
(via_rule GND)
|
||||
(rule
|
||||
(width 800.0)
|
||||
)
|
||||
(circuit
|
||||
(use_layer F.Cu B.Cu)
|
||||
)
|
||||
)
|
||||
(class Spannungen
|
||||
104
|
||||
(clearance_class Spannungen)
|
||||
(via_rule Spannungen)
|
||||
(rule
|
||||
(width 1000.0)
|
||||
)
|
||||
(circuit
|
||||
(use_layer F.Cu B.Cu)
|
||||
)
|
||||
)
|
||||
(class Steuersignale
|
||||
CS4 CLOCK MBI /IORQ /INT /M1 /RES /WR
|
||||
/RD /I1 /I2 /KAL "NMI_SW"
|
||||
(clearance_class Steuersignale)
|
||||
(via_rule Steuersignale)
|
||||
(rule
|
||||
(width 550.0)
|
||||
)
|
||||
(circuit
|
||||
(use_layer F.Cu B.Cu)
|
||||
)
|
||||
)
|
||||
)
|
||||
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|||
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|
||||
%TF.CreationDate,2023-10-18T16:20:57+02:00*%
|
||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
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|||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
G01*
|
||||
G04 APERTURE LIST*
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||||
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||||
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||||
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|
||||
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|
||||
%LPD*%
|
||||
G01*
|
||||
G04 APERTURE LIST*
|
||||
%TA.AperFunction,Profile*%
|
||||
%ADD10C,0.050000*%
|
||||
%TD*%
|
||||
G04 APERTURE END LIST*
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||||
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|
||||
X71120000Y-233500000D02*
|
||||
X71120000Y-63500000D01*
|
||||
X321120000Y-233500000D02*
|
||||
X71120000Y-233500000D01*
|
||||
X71120000Y-63500000D02*
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||||
X321120000Y-63500000D01*
|
||||
X321120000Y-63500000D02*
|
||||
X321120000Y-233500000D01*
|
||||
M02*
|
||||
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|
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@ -0,0 +1,15 @@
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|
||||
%TF.CreationDate,2023-10-18T16:20:57+02:00*%
|
||||
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|
||||
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||||
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||
G04 Created by KiCad (PCBNEW 7.0.1) date 2023-10-18 16:20:57*
|
||||
%MOMM*%
|
||||
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|
||||
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|
||||
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||||
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||||
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|
@ -0,0 +1,13 @@
|
|||
M48
|
||||
; DRILL file {KiCad 7.0.1} date Wed Oct 18 16:20:59 2023
|
||||
; FORMAT={-:-/ absolute / inch / decimal}
|
||||
; #@! TF.CreationDate,2023-10-18T16:20:59+02:00
|
||||
; #@! TF.GenerationSoftware,Kicad,Pcbnew,7.0.1
|
||||
; #@! TF.FileFunction,NonPlated,1,2,NPTH
|
||||
FMAT,2
|
||||
INCH
|
||||
%
|
||||
G90
|
||||
G05
|
||||
T0
|
||||
M30
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,125 @@
|
|||
{
|
||||
"Header": {
|
||||
"GenerationSoftware": {
|
||||
"Vendor": "KiCad",
|
||||
"Application": "Pcbnew",
|
||||
"Version": "7.0.1"
|
||||
},
|
||||
"CreationDate": "2023-10-18T16:20:57+02:00"
|
||||
},
|
||||
"GeneralSpecs": {
|
||||
"ProjectId": {
|
||||
"Name": "DLP",
|
||||
"GUID": "444c502e-6b69-4636-9164-5f7063625858",
|
||||
"Revision": "rev?"
|
||||
},
|
||||
"Size": {
|
||||
"X": 250.05,
|
||||
"Y": 170.05
|
||||
},
|
||||
"LayerNumber": 2,
|
||||
"BoardThickness": 1.6,
|
||||
"Finish": "None"
|
||||
},
|
||||
"DesignRules": [
|
||||
{
|
||||
"Layers": "Outer",
|
||||
"PadToPad": 0.0,
|
||||
"PadToTrack": 0.0,
|
||||
"TrackToTrack": 0.1,
|
||||
"MinLineWidth": 0.4
|
||||
}
|
||||
],
|
||||
"FilesAttributes": [
|
||||
{
|
||||
"Path": "DLP-F_Cu.gbr",
|
||||
"FileFunction": "Copper,L1,Top",
|
||||
"FilePolarity": "Positive"
|
||||
},
|
||||
{
|
||||
"Path": "DLP-B_Cu.gbr",
|
||||
"FileFunction": "Copper,L2,Bot",
|
||||
"FilePolarity": "Positive"
|
||||
},
|
||||
{
|
||||
"Path": "DLP-F_Paste.gbr",
|
||||
"FileFunction": "SolderPaste,Top",
|
||||
"FilePolarity": "Positive"
|
||||
},
|
||||
{
|
||||
"Path": "DLP-B_Paste.gbr",
|
||||
"FileFunction": "SolderPaste,Bot",
|
||||
"FilePolarity": "Positive"
|
||||
},
|
||||
{
|
||||
"Path": "DLP-F_Silkscreen.gbr",
|
||||
"FileFunction": "Legend,Top",
|
||||
"FilePolarity": "Positive"
|
||||
},
|
||||
{
|
||||
"Path": "DLP-B_Silkscreen.gbr",
|
||||
"FileFunction": "Legend,Bot",
|
||||
"FilePolarity": "Positive"
|
||||
},
|
||||
{
|
||||
"Path": "DLP-F_Mask.gbr",
|
||||
"FileFunction": "SolderMask,Top",
|
||||
"FilePolarity": "Negative"
|
||||
},
|
||||
{
|
||||
"Path": "DLP-B_Mask.gbr",
|
||||
"FileFunction": "SolderMask,Bot",
|
||||
"FilePolarity": "Negative"
|
||||
},
|
||||
{
|
||||
"Path": "DLP-Edge_Cuts.gbr",
|
||||
"FileFunction": "Profile",
|
||||
"FilePolarity": "Positive"
|
||||
}
|
||||
],
|
||||
"MaterialStackup": [
|
||||
{
|
||||
"Type": "Legend",
|
||||
"Name": "Top Silk Screen"
|
||||
},
|
||||
{
|
||||
"Type": "SolderPaste",
|
||||
"Name": "Top Solder Paste"
|
||||
},
|
||||
{
|
||||
"Type": "SolderMask",
|
||||
"Thickness": 0.01,
|
||||
"Name": "Top Solder Mask"
|
||||
},
|
||||
{
|
||||
"Type": "Copper",
|
||||
"Thickness": 0.035,
|
||||
"Name": "F.Cu"
|
||||
},
|
||||
{
|
||||
"Type": "Dielectric",
|
||||
"Thickness": 1.51,
|
||||
"Material": "FR4",
|
||||
"Name": "F.Cu/B.Cu",
|
||||
"Notes": "Type: dielectric layer 1 (from F.Cu to B.Cu)"
|
||||
},
|
||||
{
|
||||
"Type": "Copper",
|
||||
"Thickness": 0.035,
|
||||
"Name": "B.Cu"
|
||||
},
|
||||
{
|
||||
"Type": "SolderMask",
|
||||
"Thickness": 0.01,
|
||||
"Name": "Bottom Solder Mask"
|
||||
},
|
||||
{
|
||||
"Type": "SolderPaste",
|
||||
"Name": "Bottom Solder Paste"
|
||||
},
|
||||
{
|
||||
"Type": "Legend",
|
||||
"Name": "Bottom Silk Screen"
|
||||
}
|
||||
]
|
||||
}
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,15 @@
|
|||
%TF.GenerationSoftware,KiCad,Pcbnew,7.0.1*%
|
||||
%TF.CreationDate,2023-11-29T11:44:19+01:00*%
|
||||
%TF.ProjectId,DLP,444c502e-6b69-4636-9164-5f7063625858,rev?*%
|
||||
%TF.SameCoordinates,Original*%
|
||||
%TF.FileFunction,Paste,Bot*%
|
||||
%TF.FilePolarity,Positive*%
|
||||
%FSLAX46Y46*%
|
||||
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||
G04 Created by KiCad (PCBNEW 7.0.1) date 2023-11-29 11:44:19*
|
||||
%MOMM*%
|
||||
%LPD*%
|
||||
G01*
|
||||
G04 APERTURE LIST*
|
||||
G04 APERTURE END LIST*
|
||||
M02*
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
%TF.GenerationSoftware,KiCad,Pcbnew,7.0.1*%
|
||||
%TF.CreationDate,2023-11-29T11:44:19+01:00*%
|
||||
%TF.ProjectId,DLP,444c502e-6b69-4636-9164-5f7063625858,rev?*%
|
||||
%TF.SameCoordinates,Original*%
|
||||
%TF.FileFunction,Legend,Bot*%
|
||||
%TF.FilePolarity,Positive*%
|
||||
%FSLAX46Y46*%
|
||||
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||
G04 Created by KiCad (PCBNEW 7.0.1) date 2023-11-29 11:44:19*
|
||||
%MOMM*%
|
||||
%LPD*%
|
||||
G01*
|
||||
G04 APERTURE LIST*
|
||||
G04 APERTURE END LIST*
|
||||
M02*
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
%TF.GenerationSoftware,KiCad,Pcbnew,7.0.1*%
|
||||
%TF.CreationDate,2023-11-29T11:44:19+01:00*%
|
||||
%TF.ProjectId,DLP,444c502e-6b69-4636-9164-5f7063625858,rev?*%
|
||||
%TF.SameCoordinates,Original*%
|
||||
%TF.FileFunction,Profile,NP*%
|
||||
%FSLAX46Y46*%
|
||||
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||
G04 Created by KiCad (PCBNEW 7.0.1) date 2023-11-29 11:44:19*
|
||||
%MOMM*%
|
||||
%LPD*%
|
||||
G01*
|
||||
G04 APERTURE LIST*
|
||||
%TA.AperFunction,Profile*%
|
||||
%ADD10C,0.050000*%
|
||||
%TD*%
|
||||
G04 APERTURE END LIST*
|
||||
D10*
|
||||
X71120000Y-233500000D02*
|
||||
X71120000Y-63500000D01*
|
||||
X321120000Y-233500000D02*
|
||||
X71120000Y-233500000D01*
|
||||
X71120000Y-63500000D02*
|
||||
X321120000Y-63500000D01*
|
||||
X321120000Y-63500000D02*
|
||||
X321120000Y-233500000D01*
|
||||
M02*
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,15 @@
|
|||
%TF.GenerationSoftware,KiCad,Pcbnew,7.0.1*%
|
||||
%TF.CreationDate,2023-11-29T11:44:19+01:00*%
|
||||
%TF.ProjectId,DLP,444c502e-6b69-4636-9164-5f7063625858,rev?*%
|
||||
%TF.SameCoordinates,Original*%
|
||||
%TF.FileFunction,Paste,Top*%
|
||||
%TF.FilePolarity,Positive*%
|
||||
%FSLAX46Y46*%
|
||||
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||
G04 Created by KiCad (PCBNEW 7.0.1) date 2023-11-29 11:44:19*
|
||||
%MOMM*%
|
||||
%LPD*%
|
||||
G01*
|
||||
G04 APERTURE LIST*
|
||||
G04 APERTURE END LIST*
|
||||
M02*
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,13 @@
|
|||
M48
|
||||
; DRILL file {KiCad 7.0.1} date Wed Nov 29 11:44:28 2023
|
||||
; FORMAT={-:-/ absolute / inch / decimal}
|
||||
; #@! TF.CreationDate,2023-11-29T11:44:28+01:00
|
||||
; #@! TF.GenerationSoftware,Kicad,Pcbnew,7.0.1
|
||||
; #@! TF.FileFunction,NonPlated,1,2,NPTH
|
||||
FMAT,2
|
||||
INCH
|
||||
%
|
||||
G90
|
||||
G05
|
||||
T0
|
||||
M30
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,125 @@
|
|||
{
|
||||
"Header": {
|
||||
"GenerationSoftware": {
|
||||
"Vendor": "KiCad",
|
||||
"Application": "Pcbnew",
|
||||
"Version": "7.0.1"
|
||||
},
|
||||
"CreationDate": "2023-11-29T11:44:19+01:00"
|
||||
},
|
||||
"GeneralSpecs": {
|
||||
"ProjectId": {
|
||||
"Name": "DLP",
|
||||
"GUID": "444c502e-6b69-4636-9164-5f7063625858",
|
||||
"Revision": "rev?"
|
||||
},
|
||||
"Size": {
|
||||
"X": 250.05,
|
||||
"Y": 170.05
|
||||
},
|
||||
"LayerNumber": 2,
|
||||
"BoardThickness": 1.6,
|
||||
"Finish": "None"
|
||||
},
|
||||
"DesignRules": [
|
||||
{
|
||||
"Layers": "Outer",
|
||||
"PadToPad": 0.0,
|
||||
"PadToTrack": 0.0,
|
||||
"TrackToTrack": 0.1,
|
||||
"MinLineWidth": 0.4
|
||||
}
|
||||
],
|
||||
"FilesAttributes": [
|
||||
{
|
||||
"Path": "DLP-F_Cu.gbr",
|
||||
"FileFunction": "Copper,L1,Top",
|
||||
"FilePolarity": "Positive"
|
||||
},
|
||||
{
|
||||
"Path": "DLP-B_Cu.gbr",
|
||||
"FileFunction": "Copper,L2,Bot",
|
||||
"FilePolarity": "Positive"
|
||||
},
|
||||
{
|
||||
"Path": "DLP-F_Paste.gbr",
|
||||
"FileFunction": "SolderPaste,Top",
|
||||
"FilePolarity": "Positive"
|
||||
},
|
||||
{
|
||||
"Path": "DLP-B_Paste.gbr",
|
||||
"FileFunction": "SolderPaste,Bot",
|
||||
"FilePolarity": "Positive"
|
||||
},
|
||||
{
|
||||
"Path": "DLP-F_Silkscreen.gbr",
|
||||
"FileFunction": "Legend,Top",
|
||||
"FilePolarity": "Positive"
|
||||
},
|
||||
{
|
||||
"Path": "DLP-B_Silkscreen.gbr",
|
||||
"FileFunction": "Legend,Bot",
|
||||
"FilePolarity": "Positive"
|
||||
},
|
||||
{
|
||||
"Path": "DLP-F_Mask.gbr",
|
||||
"FileFunction": "SolderMask,Top",
|
||||
"FilePolarity": "Negative"
|
||||
},
|
||||
{
|
||||
"Path": "DLP-B_Mask.gbr",
|
||||
"FileFunction": "SolderMask,Bot",
|
||||
"FilePolarity": "Negative"
|
||||
},
|
||||
{
|
||||
"Path": "DLP-Edge_Cuts.gbr",
|
||||
"FileFunction": "Profile",
|
||||
"FilePolarity": "Positive"
|
||||
}
|
||||
],
|
||||
"MaterialStackup": [
|
||||
{
|
||||
"Type": "Legend",
|
||||
"Name": "Top Silk Screen"
|
||||
},
|
||||
{
|
||||
"Type": "SolderPaste",
|
||||
"Name": "Top Solder Paste"
|
||||
},
|
||||
{
|
||||
"Type": "SolderMask",
|
||||
"Thickness": 0.01,
|
||||
"Name": "Top Solder Mask"
|
||||
},
|
||||
{
|
||||
"Type": "Copper",
|
||||
"Thickness": 0.035,
|
||||
"Name": "F.Cu"
|
||||
},
|
||||
{
|
||||
"Type": "Dielectric",
|
||||
"Thickness": 1.51,
|
||||
"Material": "FR4",
|
||||
"Name": "F.Cu/B.Cu",
|
||||
"Notes": "Type: dielectric layer 1 (from F.Cu to B.Cu)"
|
||||
},
|
||||
{
|
||||
"Type": "Copper",
|
||||
"Thickness": 0.035,
|
||||
"Name": "B.Cu"
|
||||
},
|
||||
{
|
||||
"Type": "SolderMask",
|
||||
"Thickness": 0.01,
|
||||
"Name": "Bottom Solder Mask"
|
||||
},
|
||||
{
|
||||
"Type": "SolderPaste",
|
||||
"Name": "Bottom Solder Paste"
|
||||
},
|
||||
{
|
||||
"Type": "Legend",
|
||||
"Name": "Bottom Silk Screen"
|
||||
}
|
||||
]
|
||||
}
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
EESchema-DOCLIB Version 2.0
|
||||
#
|
||||
$CMP A302D
|
||||
D Parallel I/O, DIP-40
|
||||
K Z80 PIO parallel
|
||||
F https://www.zilog.com/appnotes_download.php?FromPage=DirectLink&dn=PS0180&ft=Product%20Specification%20(Data%20Sheet)%20%20&f=YUhSMGNEb3ZMM2QzZHk1NmFXeHZaeTVqYjIwdlpHOWpjeTk2T0RBdmNITXdNVGd3TG5Ca1pnPT0=
|
||||
$ENDCMP
|
||||
#
|
||||
$CMP AD565AJD
|
||||
D Monolithic D/A Converters
|
||||
F https://componentsearchengine.com/Datasheets/2/AD565AJD.pdf
|
||||
$ENDCMP
|
||||
#
|
||||
$CMP B315D
|
||||
D Parallel I/O, DIP-40
|
||||
K Z80 PIO parallel
|
||||
F https://www.zilog.com/appnotes_download.php?FromPage=DirectLink&dn=PS0180&ft=Product%20Specification%20(Data%20Sheet)%20%20&f=YUhSMGNEb3ZMM2QzZHk1NmFXeHZaeTVqYjIwdlpHOWpjeTk2T0RBdmNITXdNVGd3TG5Ca1pnPT0=
|
||||
$ENDCMP
|
||||
#
|
||||
$CMP UA857D
|
||||
D Parallel I/O, DIP-40
|
||||
K Z80 PIO parallel
|
||||
F https://www.zilog.com/appnotes_download.php?FromPage=DirectLink&dn=PS0180&ft=Product%20Specification%20(Data%20Sheet)%20%20&f=YUhSMGNEb3ZMM2QzZHk1NmFXeHZaeTVqYjIwdlpHOWpjeTk2T0RBdmNITXdNVGd3TG5Ca1pnPT0=
|
||||
$ENDCMP
|
||||
#
|
||||
$CMP UA857D___Z80_CTC
|
||||
D Parallel I/O, DIP-40
|
||||
K Z80 PIO parallel
|
||||
F https://www.zilog.com/appnotes_download.php?FromPage=DirectLink&dn=PS0180&ft=Product%20Specification%20(Data%20Sheet)%20%20&f=YUhSMGNEb3ZMM2QzZHk1NmFXeHZaeTVqYjIwdlpHOWpjeTk2T0RBdmNITXdNVGd3TG5Ca1pnPT0=
|
||||
$ENDCMP
|
||||
#
|
||||
$CMP UL224C35
|
||||
D Parallel I/O, DIP-40
|
||||
K Z80 PIO parallel
|
||||
F https://www.zilog.com/appnotes_download.php?FromPage=DirectLink&dn=PS0180&ft=Product%20Specification%20(Data%20Sheet)%20%20&f=YUhSMGNEb3ZMM2QzZHk1NmFXeHZaeTVqYjIwdlpHOWpjeTk2T0RBdmNITXdNVGd3TG5Ca1pnPT0=
|
||||
$ENDCMP
|
||||
#
|
||||
$CMP V4007D
|
||||
D Parallel I/O, DIP-40
|
||||
K Z80 PIO parallel
|
||||
F https://www.zilog.com/appnotes_download.php?FromPage=DirectLink&dn=PS0180&ft=Product%20Specification%20(Data%20Sheet)%20%20&f=YUhSMGNEb3ZMM2QzZHk1NmFXeHZaeTVqYjIwdlpHOWpjeTk2T0RBdmNITXdNVGd3TG5Ca1pnPT0=
|
||||
$ENDCMP
|
||||
#
|
||||
$CMP Z84C20
|
||||
D Parallel I/O, CMOS, DIP-40
|
||||
K Z80 PIO parallel
|
||||
F https://www.zilog.com/appnotes_download.php?FromPage=DirectLink&dn=PS0180&ft=Product%20Specification%20(Data%20Sheet)%20%20&f=YUhSMGNEb3ZMM2QzZHk1NmFXeHZaeTVqYjIwdlpHOWpjeTk2T0RBdmNITXdNVGd3TG5Ca1pnPT0=
|
||||
$ENDCMP
|
||||
#
|
||||
$CMP Z84C20_copy
|
||||
D Parallel I/O, CMOS, DIP-40
|
||||
K Z80 PIO parallel
|
||||
F https://www.zilog.com/appnotes_download.php?FromPage=DirectLink&dn=PS0180&ft=Product%20Specification%20(Data%20Sheet)%20%20&f=YUhSMGNEb3ZMM2QzZHk1NmFXeHZaeTVqYjIwdlpHOWpjeTk2T0RBdmNITXdNVGd3TG5Ca1pnPT0=
|
||||
$ENDCMP
|
||||
#
|
||||
$CMP Z84C20_copy1
|
||||
D Parallel I/O, CMOS, DIP-40
|
||||
K Z80 PIO parallel
|
||||
F https://www.zilog.com/appnotes_download.php?FromPage=DirectLink&dn=PS0180&ft=Product%20Specification%20(Data%20Sheet)%20%20&f=YUhSMGNEb3ZMM2QzZHk1NmFXeHZaeTVqYjIwdlpHOWpjeTk2T0RBdmNITXdNVGd3TG5Ca1pnPT0=
|
||||
$ENDCMP
|
||||
#
|
||||
$CMP Z84C20_copy1_copy
|
||||
D Parallel I/O, CMOS, DIP-40
|
||||
K Z80 PIO parallel
|
||||
F https://www.zilog.com/appnotes_download.php?FromPage=DirectLink&dn=PS0180&ft=Product%20Specification%20(Data%20Sheet)%20%20&f=YUhSMGNEb3ZMM2QzZHk1NmFXeHZaeTVqYjIwdlpHOWpjeTk2T0RBdmNITXdNVGd3TG5Ca1pnPT0=
|
||||
$ENDCMP
|
||||
#
|
||||
$CMP Z84C20_copy2
|
||||
D Parallel I/O, CMOS, DIP-40
|
||||
K Z80 PIO parallel
|
||||
F https://www.zilog.com/appnotes_download.php?FromPage=DirectLink&dn=PS0180&ft=Product%20Specification%20(Data%20Sheet)%20%20&f=YUhSMGNEb3ZMM2QzZHk1NmFXeHZaeTVqYjIwdlpHOWpjeTk2T0RBdmNITXdNVGd3TG5Ca1pnPT0=
|
||||
$ENDCMP
|
||||
#
|
||||
$CMP Z84C20_copy3
|
||||
D Parallel I/O, CMOS, DIP-40
|
||||
K Z80 PIO parallel
|
||||
F https://www.zilog.com/appnotes_download.php?FromPage=DirectLink&dn=PS0180&ft=Product%20Specification%20(Data%20Sheet)%20%20&f=YUhSMGNEb3ZMM2QzZHk1NmFXeHZaeTVqYjIwdlpHOWpjeTk2T0RBdmNITXdNVGd3TG5Ca1pnPT0=
|
||||
$ENDCMP
|
||||
#
|
||||
#End Doc Library
|
||||
|
|
@ -0,0 +1,224 @@
|
|||
EESchema-LIBRARY Version 2.4
|
||||
#encoding utf-8
|
||||
#
|
||||
# A302D
|
||||
#
|
||||
DEF A302D U 0 20 Y Y 1 F N
|
||||
F0 "U" -250 250 50 H V L BNN
|
||||
F1 "A302D" 100 250 50 H V L BNN
|
||||
F2 "Package_DIP:DIP-18_W7.62mm_Socket_LongPads" 0 -700 50 H I C CNN
|
||||
F3 "" -650 -350 50 H I C CNN
|
||||
ALIAS Z84C20_copy1
|
||||
DRAW
|
||||
S -200 200 200 -200 0 1 0 f
|
||||
X VCC 1 0 300 100 D 50 50 1 1 W
|
||||
X IN 2 -300 0 100 R 50 50 1 1 I
|
||||
X GND 3 0 -300 100 U 50 50 1 1 W
|
||||
X OUT 4 300 0 100 L 50 50 1 1 B
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# AD565AJD
|
||||
#
|
||||
DEF AD565AJD IC 0 30 Y Y 1 F N
|
||||
F0 "IC" 1250 300 50 H V L CNN
|
||||
F1 "AD565AJD" 1250 200 50 H V L CNN
|
||||
F2 "CDIP1537W58P254L3277H572Q24" 1250 100 50 H I L CNN
|
||||
F3 "https://componentsearchengine.com/Datasheets/2/AD565AJD.pdf" 1250 0 50 H I L CNN
|
||||
F4 "Monolithic D/A Converters" 1250 -100 50 H I L CNN "Description"
|
||||
F5 "5.72" 1250 -200 50 H I L CNN "Height"
|
||||
F6 "584-AD565AJD" 1250 -300 50 H I L CNN "Mouser Part Number"
|
||||
F7 "https://www.mouser.co.uk/ProductDetail/Analog-Devices/AD565AJD?qs=NmRFExCfTkHtl4TmDzzFVw%3D%3D" 1250 -400 50 H I L CNN "Mouser Price/Stock"
|
||||
F8 "Analog Devices" 1250 -500 50 H I L CNN "Manufacturer_Name"
|
||||
F9 "AD565AJD" 1250 -600 50 H I L CNN "Manufacturer_Part_Number"
|
||||
DRAW
|
||||
S 1200 100 200 -1200 0 1 0 f
|
||||
X NC_1 1 0 0 200 R 50 50 0 0 P
|
||||
X 10V_SPAN_R 10 0 -900 200 R 50 50 0 0 P
|
||||
X 20V_SPAN_R 11 0 -1000 200 R 50 50 0 0 P
|
||||
X PWR_GND 12 0 -1100 200 R 50 50 0 0 P
|
||||
X BIT_12_IN 13 1400 -1100 200 L 50 50 0 0 P
|
||||
X BIT_11_IN 14 1400 -1000 200 L 50 50 0 0 P
|
||||
X BIT_10_IN 15 1400 -900 200 L 50 50 0 0 P
|
||||
X BIT_9_IN 16 1400 -800 200 L 50 50 0 0 P
|
||||
X BIT_8_IN 17 1400 -700 200 L 50 50 0 0 P
|
||||
X BIT_7_IN 18 1400 -600 200 L 50 50 0 0 P
|
||||
X BIT_6_IN 19 1400 -500 200 L 50 50 0 0 P
|
||||
X NC_2 2 0 -100 200 R 50 50 0 0 P
|
||||
X BIT_5_IN 20 1400 -400 200 L 50 50 0 0 P
|
||||
X BIT_4_IN 21 1400 -300 200 L 50 50 0 0 P
|
||||
X BIT_3_IN 22 1400 -200 200 L 50 50 0 0 P
|
||||
X BIT_2_IN 23 1400 -100 200 L 50 50 0 0 P
|
||||
X BIT_1_IN 24 1400 0 200 L 50 50 0 0 P
|
||||
X VCC 3 0 -200 200 R 50 50 0 0 P
|
||||
X REF_OUT 4 0 -300 200 R 50 50 0 0 P
|
||||
X REF_GND 5 0 -400 200 R 50 50 0 0 P
|
||||
X REF_IN 6 0 -500 200 R 50 50 0 0 P
|
||||
X -VEE 7 0 -600 200 R 50 50 0 0 P
|
||||
X BIPOL_OFF_IN 8 0 -700 200 R 50 50 0 0 P
|
||||
X DAC_OUT 9 0 -800 200 R 50 50 0 0 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# B315D
|
||||
#
|
||||
DEF B315D U 0 20 Y Y 1 F N
|
||||
F0 "U" -100 -150 50 H V L BNN
|
||||
F1 "B315D" -150 -250 50 H V L BNN
|
||||
F2 "Package_DIP:DIP-18_W7.62mm_Socket_LongPads" 0 -400 50 H I C CNN
|
||||
F3 "" -650 -350 50 H I C CNN
|
||||
ALIAS Z84C20_copy1_copy
|
||||
DRAW
|
||||
S -300 300 300 -300 0 1 0 f
|
||||
X IN 1 400 150 100 L 50 50 1 1 I
|
||||
X OUT 10 50 400 100 D 50 50 1 1 O
|
||||
X OUT 12 150 400 100 D 50 50 1 1 O
|
||||
X IN 13 -400 -150 100 R 50 50 1 1 I
|
||||
X IN 14 400 -150 100 L 50 50 1 1 I
|
||||
X IN 2 -400 150 100 R 50 50 1 1 I
|
||||
X OUT 3 -150 400 100 D 50 50 1 1 O
|
||||
X OUT 5 -50 400 100 D 50 50 1 1 O
|
||||
X IN 6 -400 50 100 R 50 50 1 1 I
|
||||
X IN 7 400 50 100 L 50 50 1 1 I
|
||||
X IN 8 400 -50 100 L 50 50 1 1 I
|
||||
X IN 9 -400 -50 100 R 50 50 1 1 I
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# UA857D
|
||||
#
|
||||
DEF UA857D U 0 20 Y Y 1 F N
|
||||
F0 "U" -400 600 50 H V L BNN
|
||||
F1 "UA857D" 150 600 50 H V L BNN
|
||||
F2 "Package_DIP:DIP-18_W7.62mm_Socket_LongPads" 0 -700 50 H I C CNN
|
||||
F3 "" -650 -350 50 H I C CNN
|
||||
ALIAS Z84C20_copy2
|
||||
DRAW
|
||||
S -400 550 400 -1050 0 1 0 f
|
||||
X D4 1 -500 -650 100 R 50 50 1 1 B
|
||||
X ~IORQ 10 -500 150 100 R 50 50 1 1 B
|
||||
X IEO 11 500 -450 100 L 50 50 1 1 O
|
||||
X ~INT 12 -500 250 100 R 50 50 1 1 B
|
||||
X IEI 13 500 -250 100 L 50 50 1 1 I
|
||||
X ~M1~ 14 -500 -50 100 R 50 50 1 1 B
|
||||
X CP 15 -500 350 100 R 50 50 1 1 B
|
||||
X ~RES 17 -500 450 100 R 50 50 1 1 B
|
||||
X KS0 18 500 -950 100 L 50 50 1 1 O
|
||||
X VCC 18 0 650 100 D 50 50 1 1 W
|
||||
X KS1 19 500 -750 100 L 50 50 1 1 I
|
||||
X D5 2 -500 -750 100 R 50 50 1 1 B
|
||||
X C3 20 500 450 100 L 50 50 1 1 I
|
||||
X C2 21 500 350 100 L 50 50 1 1 I
|
||||
X C1 22 500 250 100 L 50 50 1 1 I
|
||||
X C0 23 500 150 100 L 50 50 1 1 I
|
||||
X D0 25 -500 -250 100 R 50 50 1 1 B
|
||||
X D1 26 -500 -350 100 R 50 50 1 1 B
|
||||
X D2 27 -500 -450 100 R 50 50 1 1 B
|
||||
X D3 28 -500 -550 100 R 50 50 1 1 B
|
||||
X D6 3 -500 -850 100 R 50 50 1 1 B
|
||||
X D7 4 -500 -950 100 R 50 50 1 1 B
|
||||
X ~RD 6 -500 50 100 R 50 50 1 1 B
|
||||
X GND 9 0 -1150 100 U 50 50 1 1 W
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# UA857D___Z80_CTC
|
||||
#
|
||||
DEF UA857D___Z80_CTC U 0 20 Y Y 1 F N
|
||||
F0 "U" -400 900 50 H V L BNN
|
||||
F1 "UA857D___Z80_CTC" 150 900 50 H V L BNN
|
||||
F2 "Package_DIP:DIP-40_W15.24mm" 0 -950 50 H I C CNN
|
||||
F3 "" 1200 -1200 50 H I C CNN
|
||||
ALIAS Z84C20_copy
|
||||
$FPLIST
|
||||
DIP*W15.24mm*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -400 850 400 -750 0 1 0 f
|
||||
X D4 1 -500 -250 100 R 50 50 1 1 I
|
||||
X ~IORQ 10 -500 450 100 R 50 50 1 1 B
|
||||
X IEO 11 500 50 100 L 50 50 1 1 B
|
||||
X ~INT 12 -500 550 100 R 50 50 1 1 B
|
||||
X IEI 13 500 250 100 L 50 50 1 1 B
|
||||
X ~M1 14 -500 250 100 R 50 50 1 1 B
|
||||
X CP 15 -500 650 100 R 50 50 1 1 B
|
||||
X ~CE 16 500 -250 100 L 50 50 1 1 B
|
||||
X ~RES 17 -500 750 100 R 50 50 1 1 B
|
||||
X KS0 18 500 -650 100 L 50 50 1 1 B
|
||||
X KS1 19 500 -450 100 L 50 50 1 1 B
|
||||
X D5 2 -500 -150 100 R 50 50 1 1 I
|
||||
X C3 20 500 750 100 L 50 50 1 1 B
|
||||
X C2 21 500 650 100 L 50 50 1 1 B
|
||||
X C1 22 500 550 100 L 50 50 1 1 B
|
||||
X C0 23 500 450 100 L 50 50 1 1 B
|
||||
X VCC 24 0 950 100 D 50 50 1 1 W
|
||||
X D0 25 -500 -650 100 R 50 50 1 1 I
|
||||
X D1 26 -500 -550 100 R 50 50 1 1 I
|
||||
X D2 27 -500 -450 100 R 50 50 1 1 I
|
||||
X D3 28 -500 -350 100 R 50 50 1 1 I
|
||||
X D6 3 -500 -50 100 R 50 50 1 1 B
|
||||
X D7 4 -500 50 100 R 50 50 1 1 B
|
||||
X GND 5 0 -850 100 U 50 50 1 1 w
|
||||
X ~RD 6 -500 350 100 R 50 50 1 1 B
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# UL224C35
|
||||
#
|
||||
DEF UL224C35 U 0 20 Y Y 1 F N
|
||||
F0 "U" -400 600 50 H V L BNN
|
||||
F1 "UL224C35" 150 600 50 H V L BNN
|
||||
F2 "Package_DIP:DIP-18_W7.62mm_Socket_LongPads" 0 -700 50 H I C CNN
|
||||
F3 "" -650 -350 50 H I C CNN
|
||||
ALIAS Z84C20
|
||||
DRAW
|
||||
S -400 550 400 -550 0 1 0 f
|
||||
X A6 1 -500 150 100 R 50 50 1 1 B
|
||||
X ~WE~ 10 500 150 100 L 50 50 1 1 B
|
||||
X D3/7 11 500 50 100 L 50 50 1 1 B
|
||||
X D2/6 12 500 -50 100 L 50 50 1 1 B
|
||||
X D1/5 13 500 -150 100 L 50 50 1 1 B
|
||||
X D0/4 14 500 -250 100 L 50 50 1 1 B
|
||||
X A9 15 -500 450 100 R 50 50 1 1 B
|
||||
X A8 16 -500 350 100 R 50 50 1 1 B
|
||||
X A7 17 -500 250 100 R 50 50 1 1 B
|
||||
X VCC 18 0 650 100 D 50 50 1 1 W
|
||||
X A5 2 -500 50 100 R 50 50 1 1 B
|
||||
X A4 3 -500 -50 100 R 50 50 1 1 B
|
||||
X A3 4 -500 -150 100 R 50 50 1 1 B
|
||||
X A2 5 -500 -450 100 R 50 50 1 1 B
|
||||
X A1 6 -500 -350 100 R 50 50 1 1 B
|
||||
X A0 7 -500 -250 100 R 50 50 1 1 B
|
||||
X ~CS~ 8 500 250 100 L 50 50 1 1 B
|
||||
X GND 9 0 -650 100 U 50 50 1 1 W
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# V4007D
|
||||
#
|
||||
DEF V4007D U 0 20 Y Y 1 F N
|
||||
F0 "U" -400 600 50 H V L BNN
|
||||
F1 "V4007D" 150 600 50 H V L BNN
|
||||
F2 "Package_DIP:DIP-18_W7.62mm_Socket_LongPads" 0 -700 50 H I C CNN
|
||||
F3 "" -650 -350 50 H I C CNN
|
||||
ALIAS Z84C20_copy3
|
||||
DRAW
|
||||
S -400 550 400 -550 0 1 0 f
|
||||
X A6 1 -500 400 100 R 50 50 1 1 B
|
||||
X ~WE~ 10 500 -100 100 L 50 50 1 1 B
|
||||
X D3/7 11 500 150 100 L 50 50 1 1 B
|
||||
X D2/6 12 -500 -350 100 R 50 50 1 1 B
|
||||
X D1/5 13 500 -200 100 L 50 50 1 1 B
|
||||
X VCC 14 0 650 100 D 50 50 1 1 W
|
||||
X A5 2 500 250 100 L 50 50 1 1 B
|
||||
X A4 3 500 400 100 L 50 50 1 1 B
|
||||
X A3 4 500 -300 100 L 50 50 1 1 B
|
||||
X A2 5 -500 200 100 R 50 50 1 1 B
|
||||
X A1 6 -500 0 100 R 50 50 1 1 B
|
||||
X GND 7 0 -650 100 U 50 50 1 1 w
|
||||
X ~CS~ 8 500 0 100 L 50 50 1 1 B
|
||||
X A0 9 500 -400 100 L 50 50 1 1 B
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
#End Library
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,5 @@
|
|||
(sym_lib_table
|
||||
(version 7)
|
||||
(lib (name "Tiracon 6V IC")(type "Legacy")(uri "${KIPRJMOD}/Tiracon 6V IC.lib")(options "")(descr ""))
|
||||
(lib (name "DLP-rescue")(type "KiCad")(uri "${KIPRJMOD}/DLP-rescue.kicad_sym")(options "")(descr ""))
|
||||
)
|
||||
|
|
@ -0,0 +1 @@
|
|||
{"hostname":"ALMAS-WAGNER","username":"Thomas Wagner"}
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,629 @@
|
|||
{
|
||||
"board": {
|
||||
"3dviewports": [],
|
||||
"design_settings": {
|
||||
"defaults": {
|
||||
"board_outline_line_width": 0.049999999999999996,
|
||||
"copper_line_width": 0.19999999999999998,
|
||||
"copper_text_italic": false,
|
||||
"copper_text_size_h": 1.5,
|
||||
"copper_text_size_v": 1.5,
|
||||
"copper_text_thickness": 0.3,
|
||||
"copper_text_upright": false,
|
||||
"courtyard_line_width": 0.049999999999999996,
|
||||
"dimension_precision": 4,
|
||||
"dimension_units": 3,
|
||||
"dimensions": {
|
||||
"arrow_length": 1270000,
|
||||
"extension_offset": 500000,
|
||||
"keep_text_aligned": true,
|
||||
"suppress_zeroes": false,
|
||||
"text_position": 0,
|
||||
"units_format": 1
|
||||
},
|
||||
"fab_line_width": 0.09999999999999999,
|
||||
"fab_text_italic": false,
|
||||
"fab_text_size_h": 1.0,
|
||||
"fab_text_size_v": 1.0,
|
||||
"fab_text_thickness": 0.15,
|
||||
"fab_text_upright": false,
|
||||
"other_line_width": 0.09999999999999999,
|
||||
"other_text_italic": false,
|
||||
"other_text_size_h": 1.0,
|
||||
"other_text_size_v": 1.0,
|
||||
"other_text_thickness": 0.15,
|
||||
"other_text_upright": false,
|
||||
"pads": {
|
||||
"drill": 1.0,
|
||||
"height": 1.7,
|
||||
"width": 1.7
|
||||
},
|
||||
"silk_line_width": 0.12,
|
||||
"silk_text_italic": false,
|
||||
"silk_text_size_h": 1.0,
|
||||
"silk_text_size_v": 1.0,
|
||||
"silk_text_thickness": 0.15,
|
||||
"silk_text_upright": false,
|
||||
"zones": {
|
||||
"min_clearance": 0.508
|
||||
}
|
||||
},
|
||||
"diff_pair_dimensions": [],
|
||||
"drc_exclusions": [],
|
||||
"meta": {
|
||||
"filename": "board_design_settings.json",
|
||||
"version": 2
|
||||
},
|
||||
"rule_severities": {
|
||||
"annular_width": "error",
|
||||
"clearance": "error",
|
||||
"connection_width": "warning",
|
||||
"copper_edge_clearance": "error",
|
||||
"copper_sliver": "warning",
|
||||
"courtyards_overlap": "error",
|
||||
"diff_pair_gap_out_of_range": "error",
|
||||
"diff_pair_uncoupled_length_too_long": "error",
|
||||
"drill_out_of_range": "error",
|
||||
"duplicate_footprints": "warning",
|
||||
"extra_footprint": "warning",
|
||||
"footprint": "error",
|
||||
"footprint_type_mismatch": "ignore",
|
||||
"hole_clearance": "error",
|
||||
"hole_near_hole": "error",
|
||||
"invalid_outline": "error",
|
||||
"isolated_copper": "warning",
|
||||
"item_on_disabled_layer": "error",
|
||||
"items_not_allowed": "error",
|
||||
"length_out_of_range": "error",
|
||||
"lib_footprint_issues": "warning",
|
||||
"lib_footprint_mismatch": "warning",
|
||||
"malformed_courtyard": "error",
|
||||
"microvia_drill_out_of_range": "error",
|
||||
"missing_courtyard": "ignore",
|
||||
"missing_footprint": "warning",
|
||||
"net_conflict": "warning",
|
||||
"npth_inside_courtyard": "ignore",
|
||||
"padstack": "warning",
|
||||
"pth_inside_courtyard": "ignore",
|
||||
"shorting_items": "error",
|
||||
"silk_edge_clearance": "warning",
|
||||
"silk_over_copper": "warning",
|
||||
"silk_overlap": "warning",
|
||||
"skew_out_of_range": "error",
|
||||
"solder_mask_bridge": "error",
|
||||
"starved_thermal": "error",
|
||||
"text_height": "warning",
|
||||
"text_thickness": "warning",
|
||||
"through_hole_pad_without_hole": "error",
|
||||
"too_many_vias": "error",
|
||||
"track_dangling": "warning",
|
||||
"track_width": "error",
|
||||
"tracks_crossing": "error",
|
||||
"unconnected_items": "error",
|
||||
"unresolved_variable": "error",
|
||||
"via_dangling": "warning",
|
||||
"zones_intersect": "error"
|
||||
},
|
||||
"rule_severitieslegacy_courtyards_overlap": true,
|
||||
"rule_severitieslegacy_no_courtyard_defined": false,
|
||||
"rules": {
|
||||
"max_error": 0.005,
|
||||
"min_clearance": 0.0,
|
||||
"min_connection": 0.0,
|
||||
"min_copper_edge_clearance": 0.024999999999999998,
|
||||
"min_hole_clearance": 0.25,
|
||||
"min_hole_to_hole": 0.25,
|
||||
"min_microvia_diameter": 0.19999999999999998,
|
||||
"min_microvia_drill": 0.09999999999999999,
|
||||
"min_resolved_spokes": 2,
|
||||
"min_silk_clearance": 0.0,
|
||||
"min_text_height": 0.7999999999999999,
|
||||
"min_text_thickness": 0.08,
|
||||
"min_through_hole_diameter": 0.3,
|
||||
"min_track_width": 0.19999999999999998,
|
||||
"min_via_annular_width": 0.09999999999999999,
|
||||
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|
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}
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue