diff --git a/P8000_WDC_Emulator/P8000_WDC_Emulator/Hardware/P8000_WDC_Emulator.pdf b/P8000_WDC_Emulator/P8000_WDC_Emulator/Hardware/P8000_WDC_Emulator.pdf index f0df6ee..c4b1470 100644 Binary files a/P8000_WDC_Emulator/P8000_WDC_Emulator/Hardware/P8000_WDC_Emulator.pdf and b/P8000_WDC_Emulator/P8000_WDC_Emulator/Hardware/P8000_WDC_Emulator.pdf differ diff --git a/P8000_WDC_Emulator/P8000_WDC_Emulator/Hardware/P8000_WDC_Emulator.sch b/P8000_WDC_Emulator/P8000_WDC_Emulator/Hardware/P8000_WDC_Emulator.sch index ee95129..04a9aeb 100755 --- a/P8000_WDC_Emulator/P8000_WDC_Emulator/Hardware/P8000_WDC_Emulator.sch +++ b/P8000_WDC_Emulator/P8000_WDC_Emulator/Hardware/P8000_WDC_Emulator.sch @@ -36,34 +36,34 @@ N 36400 54100 36000 54100 4 N 35100 54100 34700 54100 4 N 34700 54100 34700 53300 4 N 34700 53300 36400 53300 4 -C 36100 51300 1 0 1 capacitor-2.sym +C 35800 51300 1 0 1 capacitor-2.sym { -T 35900 52000 5 10 0 0 0 6 1 +T 35600 52000 5 10 0 0 0 6 1 device=POLARIZED_CAPACITOR -T 35900 51800 5 10 1 1 0 6 1 +T 35600 51800 5 10 1 1 0 6 1 refdes=2C2 -T 35900 52200 5 10 0 0 0 6 1 +T 35600 52200 5 10 0 0 0 6 1 symversion=0.1 -T 36000 51100 5 10 1 1 0 6 1 +T 35700 51100 5 10 1 1 0 6 1 value=330n } -N 36400 51500 36100 51500 4 -N 35200 51500 34800 51500 4 -C 40100 51300 1 0 1 capacitor-2.sym +N 36400 51500 35800 51500 4 +N 34900 51500 34700 51500 4 +C 40300 51300 1 0 1 capacitor-2.sym { -T 39900 52000 5 10 0 0 0 6 1 +T 40100 52000 5 10 0 0 0 6 1 device=POLARIZED_CAPACITOR -T 39900 51800 5 10 1 1 0 6 1 +T 40100 51800 5 10 1 1 0 6 1 refdes=3C2 -T 39900 52200 5 10 0 0 0 6 1 +T 40100 52200 5 10 0 0 0 6 1 symversion=0.1 -T 40000 51100 5 10 1 1 0 6 1 +T 40200 51100 5 10 1 1 0 6 1 value=330n } -N 38800 51500 39200 51500 4 -N 40100 51500 40500 51500 4 -C 34700 50400 1 0 0 gnd-1.sym -N 34800 51500 34800 50700 4 +N 38800 51500 39400 51500 4 +N 40300 51500 40500 51500 4 +C 34600 50400 1 0 0 gnd-1.sym +N 34700 51500 34700 50700 4 C 40400 50400 1 0 0 gnd-1.sym N 40500 51500 40500 50700 4 N 36400 54300 36200 54300 4 @@ -100,9 +100,6 @@ N 41100 51200 41100 52100 4 N 47300 54800 43100 54800 4 N 43100 54800 43100 60700 4 N 43100 60700 64300 60700 4 -N 47300 55400 43700 55400 4 -N 43700 55400 43700 60100 4 -N 43700 60100 54100 60100 4 N 47300 55100 43400 55100 4 N 43400 55100 43400 60400 4 N 43400 60400 54400 60400 4 @@ -174,7 +171,7 @@ T 67100 33100 9 8 1 0 0 0 1 T 68500 33100 9 8 1 0 0 0 1 1 T 71000 33400 9 7 1 0 0 0 1 -$Revision: 1.17 $ / $Date: 2012/06/16 19:34:40 $ +$Revision: 1.18 $ / $Date: 2012/06/18 20:04:16 $ T 71000 33100 9 8 1 0 0 0 1 Oliver Lehmann N 50600 59400 51200 59400 4 @@ -183,9 +180,9 @@ N 50600 62800 51800 62800 4 N 49100 62800 49600 62800 4 N 49100 62800 49100 62500 4 C 49000 62200 1 0 0 gnd-1.sym -N 57400 59400 59800 59400 4 -N 57400 58100 63000 58100 4 -N 57400 56800 63300 56800 4 +N 58600 58600 59800 58600 4 +N 58600 58100 63000 58100 4 +N 58600 57600 63300 57600 4 C 64300 60600 1 0 0 io-1.sym { T 64500 61200 5 10 0 0 0 0 1 @@ -240,14 +237,12 @@ X3 N 64300 60100 59800 60100 4 N 64300 59200 63000 59200 4 N 64300 58900 63300 58900 4 -N 54700 59400 54700 61000 4 -N 56500 59400 54700 59400 4 -N 56500 58100 54400 58100 4 +N 54700 58600 54700 61000 4 +N 56200 58600 54700 58600 4 +N 56200 58100 54400 58100 4 N 54400 58100 54400 60400 4 -N 56500 56800 54100 56800 4 -N 54100 56800 54100 60100 4 N 64300 60400 62700 60400 4 -N 62700 60400 62700 57600 4 +N 62700 60400 62700 57000 4 N 64300 59500 62700 59500 4 C 61400 59600 1 90 1 capacitor-2.sym { @@ -277,9 +272,9 @@ N 61200 59600 61200 61500 4 N 61200 58700 61200 58400 4 N 61200 58400 62700 58400 4 N 62000 58700 62000 58400 4 -C 62800 57300 1 0 1 gnd-1.sym +C 62800 56700 1 0 1 gnd-1.sym N 63000 58100 63000 59200 4 -N 63300 56800 63300 58900 4 +N 63300 57600 63300 58900 4 C 47200 48800 1 0 0 atmega1284p.sym { T 50300 59700 5 10 1 1 0 6 1 @@ -289,67 +284,17 @@ device=Atmega1284P T 47600 55700 5 10 0 0 0 0 1 footprint=DIP_40 } -C 57400 59500 1 180 0 resistor-1.sym -{ -T 57100 59100 5 10 0 0 180 0 1 -device=RESISTOR -T 56800 59600 5 10 1 1 0 0 1 -refdes=1R1 -T 56800 59100 5 10 1 1 0 0 1 -value=1k8 -} -C 57400 58200 1 180 0 resistor-1.sym -{ -T 57100 57800 5 10 0 0 180 0 1 -device=RESISTOR -T 56800 58300 5 10 1 1 0 0 1 -refdes=2R1 -T 56800 57800 5 10 1 1 0 0 1 -value=1k8 -} C 57400 56900 1 180 0 resistor-1.sym { T 57100 56500 5 10 0 0 180 0 1 device=RESISTOR -T 56800 57000 5 10 1 1 0 0 1 -refdes=3R1 T 56800 56500 5 10 1 1 0 0 1 value=1k8 } N 59800 55400 59800 60100 4 C 61000 61500 1 0 0 3.3V-plus-1.sym -N 60800 58100 60800 55400 4 -N 61800 56800 61800 55400 4 -C 59900 54500 1 90 0 resistor-1.sym -{ -T 59500 54800 5 10 0 0 90 0 1 -device=RESISTOR -T 60000 55000 5 10 1 1 0 0 1 -refdes=1R2 -T 60000 54800 5 10 1 1 0 0 1 -value=3k3 -} -C 60900 54500 1 90 0 resistor-1.sym -{ -T 60500 54800 5 10 0 0 90 0 1 -device=RESISTOR -T 61000 55000 5 10 1 1 0 0 1 -refdes=2R2 -T 61000 54800 5 10 1 1 0 0 1 -value=3k3 -} -C 61900 54500 1 90 0 resistor-1.sym -{ -T 61500 54800 5 10 0 0 90 0 1 -device=RESISTOR -T 62000 55000 5 10 1 1 0 0 1 -refdes=3R2 -T 62000 54800 5 10 1 1 0 0 1 -value=3k3 -} -N 59800 54500 59800 53900 4 -N 61800 53900 61800 54500 4 -N 60800 54500 60800 53900 4 +N 60100 58100 60100 55400 4 +N 60400 57600 60400 55400 4 C 51800 56600 1 90 0 crystal-1.sym { T 51300 56800 5 10 0 0 90 0 1 @@ -699,9 +644,9 @@ pinlabel=\_RST\_ N 47300 51800 42000 51800 4 N 41100 46600 47900 46600 4 T 41200 46800 9 10 1 0 0 0 1 -/RDWR TO ATA +/RDWRTOATA T 41200 41100 9 10 1 0 0 0 1 -/ACCESS LATCH +/ACCESSLATCH C 37300 43900 1 0 1 74245-1.sym { T 37000 47250 5 10 0 0 0 6 1 @@ -1011,13 +956,10 @@ N 30600 41200 30600 39400 4 N 31300 40900 30600 40900 4 N 31300 40600 30600 40600 4 N 31300 40300 30600 40300 4 -T 40000 39000 9 10 1 0 0 6 1 -SYSCONF +T 39400 39000 9 10 1 0 0 0 1 +/SYSCONF T 39400 44500 9 10 1 0 0 0 1 -P8000COM -N 59800 53900 61800 53900 4 -N 60800 53900 60800 53400 4 -C 60900 53100 1 0 1 gnd-1.sym +/P8000COM C 66000 38200 1 0 1 header40-2.sym { T 65750 46700 5 10 0 1 0 6 1 @@ -1211,7 +1153,7 @@ N 64600 40400 63500 40400 4 T 64600 40500 5 10 1 1 0 6 1 pinlabel=GND } -N 63500 46000 63500 37000 4 +N 63500 46000 63500 36700 4 N 64600 42000 63500 42000 4 { T 64600 42100 5 10 1 1 0 6 1 @@ -1253,7 +1195,7 @@ N 71300 40800 71300 41500 4 C 71500 41500 1 0 1 5V-plus-1.sym N 67900 41600 67900 35700 4 N 54800 40800 60600 40800 4 -C 63600 36700 1 0 1 gnd-1.sym +C 63600 36400 1 0 1 gnd-1.sym N 67500 35300 67500 41200 4 N 50300 35300 67500 35300 4 N 62700 39200 62700 37500 4 @@ -1310,14 +1252,14 @@ C 69800 39600 1 0 0 busripper-1.sym T 69800 40000 5 8 0 0 0 0 1 device=none T 69700 39700 5 10 1 1 0 6 1 -pinlabel=DA2 +pinlabel=DA1 } C 69800 37500 1 0 0 busripper-1.sym { T 69800 37900 5 8 0 0 0 0 1 device=none T 69700 37600 5 10 1 1 0 6 1 -pinlabel=DA1 +pinlabel=DA2 } C 69800 37900 1 0 0 busripper-1.sym { @@ -2088,3 +2030,271 @@ device=LED N 40400 36000 40400 35700 4 C 40200 37600 1 0 0 5V-plus-1.sym N 40400 36900 40400 37600 4 +N 67100 42400 67100 37100 4 +N 67100 37100 63500 37100 4 +N 66600 42000 66000 42000 4 +{ +T 66000 42100 5 10 1 1 0 0 1 +pinlabel=DMARQ +} +N 67100 42400 66000 42400 4 +{ +T 66000 42500 5 10 1 1 0 0 1 +pinlabel=GND +} +T 63900 42500 9 10 1 0 0 0 1 +(keypin) +N 41600 43400 40700 43400 4 +N 40700 43400 40700 47800 4 +N 40700 47800 55400 47800 4 +N 55400 47800 55400 57600 4 +N 55400 57600 56200 57600 4 +T 41200 48000 9 10 1 0 0 0 1 +/MCCEN +C 46800 55300 1 0 0 nc-left-1.sym +{ +T 46800 55700 5 10 0 0 0 0 1 +value=NoConnection +T 46800 56100 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 46800 52900 1 0 0 nc-left-1.sym +{ +T 46800 53300 5 10 0 0 0 0 1 +value=NoConnection +T 46800 53700 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 35900 52400 1 0 0 nc-left-1.sym +{ +T 35900 52800 5 10 0 0 0 0 1 +value=NoConnection +T 35900 53200 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 35900 51600 1 0 0 nc-left-1.sym +{ +T 35900 52000 5 10 0 0 0 0 1 +value=NoConnection +T 35900 52400 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 41100 43000 1 0 0 nc-left-1.sym +{ +T 41100 43400 5 10 0 0 0 0 1 +value=NoConnection +T 41100 43800 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 41100 42700 1 0 0 nc-left-1.sym +{ +T 41100 43100 5 10 0 0 0 0 1 +value=NoConnection +T 41100 43500 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 41100 44500 1 0 0 nc-left-1.sym +{ +T 41100 44900 5 10 0 0 0 0 1 +value=NoConnection +T 41100 45300 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 63500 40700 1 0 0 nc-left-1.sym +{ +T 63500 41100 5 10 0 0 0 0 1 +value=NoConnection +T 63500 41500 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 63500 39900 1 0 0 nc-left-1.sym +{ +T 63500 40300 5 10 0 0 0 0 1 +value=NoConnection +T 63500 40700 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 63500 39500 1 0 0 nc-left-1.sym +{ +T 63500 39900 5 10 0 0 0 0 1 +value=NoConnection +T 63500 40300 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 66600 39900 1 0 0 nc-right-1.sym +{ +T 66700 40400 5 10 0 0 0 0 1 +value=NoConnection +T 66700 40600 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 66600 40700 1 0 0 nc-right-1.sym +{ +T 66700 41200 5 10 0 0 0 0 1 +value=NoConnection +T 66700 41400 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 66600 41900 1 0 0 nc-right-1.sym +{ +T 66700 42400 5 10 0 0 0 0 1 +value=NoConnection +T 66700 42600 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 38800 52400 1 0 0 nc-right-1.sym +{ +T 38900 52900 5 10 0 0 0 0 1 +value=NoConnection +T 38900 53100 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 38800 51600 1 0 0 nc-right-1.sym +{ +T 38900 52100 5 10 0 0 0 0 1 +value=NoConnection +T 38900 52300 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 31900 53600 1 0 0 nc-right-1.sym +{ +T 32000 54100 5 10 0 0 0 0 1 +value=NoConnection +T 32000 54300 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 31900 53300 1 0 0 nc-right-1.sym +{ +T 32000 53800 5 10 0 0 0 0 1 +value=NoConnection +T 32000 54000 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 31900 52700 1 0 0 nc-right-1.sym +{ +T 32000 53200 5 10 0 0 0 0 1 +value=NoConnection +T 32000 53400 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 31900 52100 1 0 0 nc-right-1.sym +{ +T 32000 52600 5 10 0 0 0 0 1 +value=NoConnection +T 32000 52800 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 31900 51800 1 0 0 nc-right-1.sym +{ +T 32000 52300 5 10 0 0 0 0 1 +value=NoConnection +T 32000 52500 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 31900 51500 1 0 0 nc-right-1.sym +{ +T 32000 52000 5 10 0 0 0 0 1 +value=NoConnection +T 32000 52200 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 31900 56000 1 0 0 nc-right-1.sym +{ +T 32000 56500 5 10 0 0 0 0 1 +value=NoConnection +T 32000 56700 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 31900 56600 1 0 0 nc-right-1.sym +{ +T 32000 57100 5 10 0 0 0 0 1 +value=NoConnection +T 32000 57300 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 31900 57200 1 0 0 nc-right-1.sym +{ +T 32000 57700 5 10 0 0 0 0 1 +value=NoConnection +T 32000 57900 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 31900 57500 1 0 0 nc-right-1.sym +{ +T 32000 58000 5 10 0 0 0 0 1 +value=NoConnection +T 32000 58200 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 31900 59000 1 0 0 nc-right-1.sym +{ +T 32000 59500 5 10 0 0 0 0 1 +value=NoConnection +T 32000 59700 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 31900 59300 1 0 0 nc-right-1.sym +{ +T 32000 59800 5 10 0 0 0 0 1 +value=NoConnection +T 32000 60000 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 31900 59900 1 0 0 nc-right-1.sym +{ +T 32000 60400 5 10 0 0 0 0 1 +value=NoConnection +T 32000 60600 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 31900 60200 1 0 0 nc-right-1.sym +{ +T 32000 60700 5 10 0 0 0 0 1 +value=NoConnection +T 32000 60900 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 59700 55400 1 180 1 resistorpack5-1.sym +{ +T 59800 54000 5 10 0 0 180 6 1 +device=RESISTORPACK_5 +T 59800 54200 5 10 1 1 180 6 1 +refdes=R2 +T 60500 54200 5 10 1 1 180 6 1 +value=3k3 +} +C 61900 53600 1 0 1 gnd-1.sym +N 61200 54300 61800 54300 4 +N 61800 54300 61800 53900 4 +C 56200 56800 1 0 0 rpack4-1.sym +{ +T 56295 59900 5 10 0 0 0 0 1 +device=rpack4 +T 56295 59700 5 10 0 0 0 0 1 +footprint=0603_rpack4 +T 57795 58900 5 10 1 1 0 0 1 +refdes=R1 +T 56200 56800 5 10 1 1 0 0 1 +value=1k8 +} +C 55700 57000 1 0 0 nc-left-1.sym +{ +T 55700 57400 5 10 0 0 0 0 1 +value=NoConnection +T 55700 57800 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 50600 52900 1 0 0 nc-right-1.sym +{ +T 50700 53400 5 10 0 0 0 0 1 +value=NoConnection +T 50700 53600 5 10 0 0 0 0 1 +device=DRC_Directive +} +C 58600 57000 1 0 0 nc-right-1.sym +{ +T 58700 57500 5 10 0 0 0 0 1 +value=NoConnection +T 58700 57700 5 10 0 0 0 0 1 +device=DRC_Directive +} diff --git a/P8000_WDC_Emulator/P8000_WDC_Emulator/Hardware/atmega1284p.sym b/P8000_WDC_Emulator/P8000_WDC_Emulator/Hardware/atmega1284p.sym new file mode 100755 index 0000000..ac7570f --- /dev/null +++ b/P8000_WDC_Emulator/P8000_WDC_Emulator/Hardware/atmega1284p.sym @@ -0,0 +1,467 @@ +v 20091004 2 +P 3400 4200 3100 4200 1 0 0 +{ +T 3200 4250 5 8 1 1 0 0 1 +pinnumber=32 +T 3200 4150 5 8 0 1 0 2 1 +pinseq=24 +T 3050 4200 9 8 1 1 0 6 1 +pinlabel=AREF +T 3050 4200 5 8 0 1 0 8 1 +pintype=pwr +} +P 3400 3900 3100 3900 1 0 0 +{ +T 3200 3950 5 8 1 1 0 0 1 +pinnumber=30 +T 3200 3850 5 8 0 1 0 2 1 +pinseq=23 +T 3050 3900 9 8 1 1 0 6 1 +pinlabel=AVCC +T 3050 3900 5 8 0 1 0 8 1 +pintype=pwr +} +P 3400 10600 3200 10600 1 0 0 +{ +T 3200 10650 5 8 1 1 0 0 1 +pinnumber=9 +T 3200 10550 5 8 0 1 0 2 1 +pinseq=4 +T 3050 10600 9 8 1 1 0 6 1 +pinlabel=\_RESET\_ +T 3050 10600 5 8 0 1 0 8 1 +pintype=in +} +V 3150 10600 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 3400 8300 3100 8300 1 0 0 +{ +T 3200 8350 5 8 1 1 0 0 1 +pinnumber=13 +T 3200 8250 5 8 0 1 0 2 1 +pinseq=6 +T 2975 8300 9 8 1 1 0 6 1 +pinlabel=XTAL1 +T 2975 8300 5 8 0 1 0 8 1 +pintype=clk +} +L 3000 8300 3100 8225 3 0 0 0 -1 -1 +L 3000 8300 3100 8375 3 0 0 0 -1 -1 +P 3400 8000 3100 8000 1 0 0 +{ +T 3200 8050 5 8 1 1 0 0 1 +pinnumber=12 +T 3200 7950 5 8 0 1 0 2 1 +pinseq=5 +T 2975 8000 9 8 1 1 0 6 1 +pinlabel=XTAL2 +T 2975 8000 5 8 0 1 0 8 1 +pintype=clk +} +L 3000 8000 3100 7925 3 0 0 0 -1 -1 +L 3000 8000 3100 8075 3 0 0 0 -1 -1 +P 100 7800 400 7800 1 0 0 +{ +T 300 7850 5 8 1 1 0 6 1 +pinnumber=1 +T 300 7750 5 8 0 1 0 8 1 +pinseq=33 +T 450 7800 9 8 1 1 0 0 1 +pinlabel=PB0 (XCK0/T0/PCINT8) +T 450 7800 5 8 0 1 0 2 1 +pintype=io +} +P 100 7500 400 7500 1 0 0 +{ +T 300 7550 5 8 1 1 0 6 1 +pinnumber=2 +T 300 7450 5 8 0 1 0 8 1 +pinseq=34 +T 450 7500 9 8 1 1 0 0 1 +pinlabel=PB1 (T1/CLKO/PCINT9) +T 450 7500 5 8 0 1 0 2 1 +pintype=io +} +P 100 7200 400 7200 1 0 0 +{ +T 300 7250 5 8 1 1 0 6 1 +pinnumber=3 +T 300 7150 5 8 0 1 0 8 1 +pinseq=35 +T 450 7200 9 8 1 1 0 0 1 +pinlabel=PB2 (AIN0/INT2/PCINT10) +T 450 7200 5 8 0 1 0 2 1 +pintype=io +} +P 100 6900 400 6900 1 0 0 +{ +T 300 6950 5 8 1 1 0 6 1 +pinnumber=4 +T 300 6850 5 8 0 1 0 8 1 +pinseq=36 +T 450 6900 9 8 1 1 0 0 1 +pinlabel=PB3 (AIN1/OC0A/PCINT11) +T 450 6900 5 8 0 1 0 2 1 +pintype=io +} +P 100 6600 400 6600 1 0 0 +{ +T 300 6650 5 8 1 1 0 6 1 +pinnumber=5 +T 300 6550 5 8 0 1 0 8 1 +pinseq=37 +T 450 6600 9 8 1 1 0 0 1 +pinlabel=PB4 (\_SS\_/OC0B/PCINT12) +T 450 6600 5 8 0 1 0 2 1 +pintype=io +} +P 100 6300 400 6300 1 0 0 +{ +T 300 6350 5 8 1 1 0 6 1 +pinnumber=6 +T 300 6250 5 8 0 1 0 8 1 +pinseq=1 +T 450 6300 9 8 1 1 0 0 1 +pinlabel=PB5 (PCINT13/MOSI) +T 450 6300 5 8 0 1 0 2 1 +pintype=io +} +P 100 6000 400 6000 1 0 0 +{ +T 300 6050 5 8 1 1 0 6 1 +pinnumber=7 +T 300 5950 5 8 0 1 0 8 1 +pinseq=2 +T 450 6000 9 8 1 1 0 0 1 +pinlabel=PB6 (PCINT14/MISO) +T 450 6000 5 8 0 1 0 2 1 +pintype=io +} +P 100 5700 400 5700 1 0 0 +{ +T 300 5750 5 8 1 1 0 6 1 +pinnumber=8 +T 300 5650 5 8 0 1 0 8 1 +pinseq=3 +T 450 5700 9 8 1 1 0 0 1 +pinlabel=PB7 (PCINT15/SCK) +T 450 5700 5 8 0 1 0 2 1 +pintype=io +} +P 100 5100 400 5100 1 0 0 +{ +T 300 5150 5 8 1 1 0 6 1 +pinnumber=22 +T 300 5050 5 8 0 1 0 8 1 +pinseq=15 +T 450 5100 9 8 1 1 0 0 1 +pinlabel=PC0 (PCINT16/SCL) +T 450 5100 5 8 0 1 0 2 1 +pintype=io +} +P 100 4800 400 4800 1 0 0 +{ +T 300 4850 5 8 1 1 0 6 1 +pinnumber=23 +T 300 4750 5 8 0 1 0 8 1 +pinseq=16 +T 450 4800 9 8 1 1 0 0 1 +pinlabel=PC1 (PCINT17/SDA) +T 450 4800 5 8 0 1 0 2 1 +pintype=io +} +P 100 4500 400 4500 1 0 0 +{ +T 300 4550 5 8 1 1 0 6 1 +pinnumber=24 +T 300 4450 5 8 0 1 0 8 1 +pinseq=17 +T 450 4500 9 8 1 1 0 0 1 +pinlabel=PC2 (PCINT18/TCK) +T 450 4500 5 8 0 1 0 2 1 +pintype=io +} +P 100 4200 400 4200 1 0 0 +{ +T 300 4250 5 8 1 1 0 6 1 +pinnumber=25 +T 300 4150 5 8 0 1 0 8 1 +pinseq=18 +T 450 4200 9 8 1 1 0 0 1 +pinlabel=PC3 (PCINT19/TMS) +T 450 4200 5 8 0 1 0 2 1 +pintype=io +} +P 100 3900 400 3900 1 0 0 +{ +T 300 3950 5 8 1 1 0 6 1 +pinnumber=26 +T 300 3850 5 8 0 1 0 8 1 +pinseq=19 +T 450 3900 9 8 1 1 0 0 1 +pinlabel=PC4 (TDO/PCINT20) +T 450 3900 5 8 0 1 0 2 1 +pintype=io +} +P 100 3600 400 3600 1 0 0 +{ +T 300 3650 5 8 1 1 0 6 1 +pinnumber=27 +T 300 3550 5 8 0 1 0 8 1 +pinseq=20 +T 450 3600 9 8 1 1 0 0 1 +pinlabel=PC5 (TDI/PCINT21) +T 450 3600 5 8 0 1 0 2 1 +pintype=io +} +P 100 3300 400 3300 1 0 0 +{ +T 300 3350 5 8 1 1 0 6 1 +pinnumber=28 +T 300 3250 5 8 0 1 0 8 1 +pinseq=21 +T 450 3300 9 8 1 1 0 0 1 +pinlabel=PC6 (TOSC1/PCINT22) +T 450 3300 5 8 0 1 0 2 1 +pintype=io +} +P 100 3000 400 3000 1 0 0 +{ +T 300 3050 5 8 1 1 0 6 1 +pinnumber=29 +T 300 2950 5 8 0 1 0 8 1 +pinseq=22 +T 450 3000 9 8 1 1 0 0 1 +pinlabel=PC7 (TOSC2/PCINT23) +T 450 3000 5 8 0 1 0 2 1 +pintype=io +} +P 100 2400 400 2400 1 0 0 +{ +T 300 2450 5 8 1 1 0 6 1 +pinnumber=14 +T 300 2350 5 8 0 1 0 8 1 +pinseq=7 +T 450 2400 9 8 1 1 0 0 1 +pinlabel=PD0 (PCINT24/RXD0) +T 450 2400 5 8 0 1 0 2 1 +pintype=io +} +P 100 2100 400 2100 1 0 0 +{ +T 300 2150 5 8 1 1 0 6 1 +pinnumber=15 +T 300 2050 5 8 0 1 0 8 1 +pinseq=8 +T 450 2100 9 8 1 1 0 0 1 +pinlabel=PD1 (PCINT25/TXD0) +T 450 2100 5 8 0 1 0 2 1 +pintype=io +} +P 100 1800 400 1800 1 0 0 +{ +T 300 1850 5 8 1 1 0 6 1 +pinnumber=16 +T 300 1750 5 8 0 1 0 8 1 +pinseq=9 +T 450 1800 9 8 1 1 0 0 1 +pinlabel=PD2 (PCINT26/RXD1/INT0) +T 450 1800 5 8 0 1 0 2 1 +pintype=io +} +P 100 1500 400 1500 1 0 0 +{ +T 300 1550 5 8 1 1 0 6 1 +pinnumber=17 +T 300 1450 5 8 0 1 0 8 1 +pinseq=10 +T 450 1500 9 8 1 1 0 0 1 +pinlabel=PD3 (PCINT27/TXD1/INT1) +T 450 1500 5 8 0 1 0 2 1 +pintype=io +} +P 100 1200 400 1200 1 0 0 +{ +T 300 1250 5 8 1 1 0 6 1 +pinnumber=18 +T 300 1150 5 8 0 1 0 8 1 +pinseq=11 +T 450 1200 9 8 1 1 0 0 1 +pinlabel=PD4 (PCINT28/XCK1/OC1B) +T 450 1200 5 8 0 1 0 2 1 +pintype=io +} +P 100 900 400 900 1 0 0 +{ +T 300 950 5 8 1 1 0 6 1 +pinnumber=19 +T 300 850 5 8 0 1 0 8 1 +pinseq=12 +T 450 900 9 8 1 1 0 0 1 +pinlabel=PD5 (PCINT29/OC1A) +T 450 900 5 8 0 1 0 2 1 +pintype=io +} +P 100 600 400 600 1 0 0 +{ +T 300 650 5 8 1 1 0 6 1 +pinnumber=20 +T 300 550 5 8 0 1 0 8 1 +pinseq=13 +T 450 600 9 8 1 1 0 0 1 +pinlabel=PD6 (PCINT30/OC2B/ICP) +T 450 600 5 8 0 1 0 2 1 +pintype=io +} +P 100 300 400 300 1 0 0 +{ +T 300 350 5 8 1 1 0 6 1 +pinnumber=21 +T 300 250 5 8 0 1 0 8 1 +pinseq=14 +T 450 300 9 8 1 1 0 0 1 +pinlabel=PD7 (PCINT31/OC2A) +T 450 300 5 8 0 1 0 2 1 +pintype=io +} +B 400 100 2700 10700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 3100 10900 8 10 1 1 0 6 1 +refdes=U? +T 400 10900 9 10 1 0 0 0 1 +ATmega1284P +T 400 7700 5 10 0 0 0 0 1 +device=Atmega1284P +T 400 6900 5 10 0 0 0 0 1 +footprint=DIP_40 +T 400 6300 5 10 0 0 0 0 1 +author=Anton Dubniak +T 400 7300 5 10 0 0 0 0 1 +documentation=http://www.atmel.com/Images/doc8059.pdf +T 400 7500 5 10 0 0 0 0 1 +description=8-bit RISC micro-controller (Atmel) +T 400 6700 5 10 0 0 0 0 1 +numslots=0 +T 400 6100 5 10 0 0 0 0 1 +dist-license=GPL +T 400 5900 5 10 0 0 0 0 1 +use-license=unlimited +P 100 10600 400 10600 1 0 0 +{ +T 305 10645 5 8 1 1 0 6 1 +pinnumber=40 +T 300 10550 5 8 0 1 0 8 1 +pinseq=32 +T 455 10595 9 8 1 1 0 0 1 +pinlabel=PA0 (ADC0/PCINT0) +T 450 10600 5 8 0 1 0 2 1 +pintype=io +} +P 100 10300 400 10300 1 0 0 +{ +T 305 10345 5 8 1 1 0 6 1 +pinnumber=39 +T 300 10250 5 8 0 1 0 8 1 +pinseq=31 +T 455 10295 9 8 1 1 0 0 1 +pinlabel=PA1 (ADC1/PCINT1) +T 450 10300 5 8 0 1 0 2 1 +pintype=io +} +P 100 10000 400 10000 1 0 0 +{ +T 305 10045 5 8 1 1 0 6 1 +pinnumber=38 +T 300 9950 5 8 0 1 0 8 1 +pinseq=30 +T 455 9995 9 8 1 1 0 0 1 +pinlabel=PA2 (ADC2/PCINT2) +T 450 10000 5 8 0 1 0 2 1 +pintype=io +} +P 100 9700 400 9700 1 0 0 +{ +T 305 9745 5 8 1 1 0 6 1 +pinnumber=37 +T 300 9650 5 8 0 1 0 8 1 +pinseq=29 +T 455 9695 9 8 1 1 0 0 1 +pinlabel=PA3 (ADC3/PCINT3) +T 450 9700 5 8 0 1 0 2 1 +pintype=io +} +P 100 9400 400 9400 1 0 0 +{ +T 305 9445 5 8 1 1 0 6 1 +pinnumber=36 +T 300 9350 5 8 0 1 0 8 1 +pinseq=28 +T 455 9395 9 8 1 1 0 0 1 +pinlabel=PA4 (ADC4/PCINT4) +T 450 9400 5 8 0 1 0 2 1 +pintype=io +} +P 100 9100 400 9100 1 0 0 +{ +T 305 9145 5 8 1 1 0 6 1 +pinnumber=35 +T 300 9050 5 8 0 1 0 8 1 +pinseq=27 +T 455 9095 9 8 1 1 0 0 1 +pinlabel=PA5 (ADC5/PCINT5) +T 450 9100 5 8 0 1 0 2 1 +pintype=io +} +P 100 8800 400 8800 1 0 0 +{ +T 305 8845 5 8 1 1 0 6 1 +pinnumber=34 +T 300 8750 5 8 0 1 0 8 1 +pinseq=26 +T 455 8795 9 8 1 1 0 0 1 +pinlabel=PA6 (ADC6/PCINT6) +T 450 8800 5 8 0 1 0 2 1 +pintype=io +} +P 100 8500 400 8500 1 0 0 +{ +T 305 8545 5 8 1 1 0 6 1 +pinnumber=33 +T 300 8450 5 8 0 1 0 8 1 +pinseq=25 +T 455 8495 9 8 1 1 0 0 1 +pinlabel=PA7 (ADC7/PCINT7) +T 450 8500 5 8 0 1 0 2 1 +pintype=io +} +P 3400 1200 3100 1200 1 0 0 +{ +T 3200 1250 5 8 1 1 0 0 1 +pinnumber=11 +T 3200 1150 5 8 0 1 0 2 1 +pinseq=6 +T 3050 1200 9 8 1 1 0 6 1 +pinlabel=GND +T 3050 1200 5 8 0 1 0 8 1 +pintype=pwr +} +P 3400 900 3100 900 1 0 0 +{ +T 3200 950 5 8 1 1 0 0 1 +pinnumber=31 +T 3200 850 5 8 0 1 0 2 1 +pinseq=18 +T 3050 900 9 8 1 1 0 6 1 +pinlabel=GND +T 3050 900 5 8 0 1 0 8 1 +pintype=pwr +} +P 3400 3600 3100 3600 1 0 0 +{ +T 3200 3650 5 8 1 1 0 0 1 +pinnumber=10 +T 3200 3550 5 8 0 1 0 2 1 +pinseq=5 +T 3050 3600 9 8 1 1 0 6 1 +pinlabel=VCC +T 3050 3600 5 8 0 1 0 8 1 +pintype=pwr +} diff --git a/P8000_WDC_Emulator/P8000_WDC_Emulator/Hardware/max3232.sym b/P8000_WDC_Emulator/P8000_WDC_Emulator/Hardware/max3232.sym new file mode 100755 index 0000000..b3e80c6 --- /dev/null +++ b/P8000_WDC_Emulator/P8000_WDC_Emulator/Hardware/max3232.sym @@ -0,0 +1,136 @@ +v 20050313 1 +P 2100 3200 2400 3200 1 0 1 +{ +T 2150 3250 5 8 1 1 0 0 1 +pinnumber=16 +T 2000 3200 5 8 1 1 0 6 1 +pinlabel=VCC +} +P 2100 200 2400 200 1 0 1 +{ +T 2150 250 5 8 1 1 0 0 1 +pinnumber=15 +T 2000 200 5 8 1 1 0 6 1 +pinlabel=GND +} +P 2100 1800 2400 1800 1 0 1 +{ +T 2150 1850 5 8 1 1 0 0 1 +pinnumber=14 +} +P 2100 1000 2400 1000 1 0 1 +{ +T 2150 1050 5 8 1 1 0 0 1 +pinnumber=13 +} +P 300 1000 0 1000 1 0 1 +{ +T 250 1050 5 8 1 1 0 6 1 +pinnumber=12 +} +P 300 1800 0 1800 1 0 1 +{ +T 250 1850 5 8 1 1 0 6 1 +pinnumber=11 +} +P 300 1400 0 1400 1 0 1 +{ +T 250 1450 5 8 1 1 0 6 1 +pinnumber=10 +} +P 300 600 0 600 1 0 1 +{ +T 250 650 5 8 1 1 0 6 1 +pinnumber=9 +} +P 300 3000 0 3000 1 0 1 +{ +T 250 3050 5 8 1 1 0 6 1 +pinnumber=1 +T 400 3000 5 8 1 1 0 0 1 +pinlabel=C1+ +} +P 2100 400 2400 400 1 0 1 +{ +T 2150 450 5 8 1 1 0 0 1 +pinnumber=2 +T 2000 400 5 8 1 1 0 6 1 +pinlabel=V+ +} +P 300 2200 0 2200 1 0 1 +{ +T 250 2250 5 8 1 1 0 6 1 +pinnumber=3 +T 400 2200 5 8 1 1 0 0 1 +pinlabel=C1- +} +P 2100 3000 2400 3000 1 0 1 +{ +T 2150 3050 5 8 1 1 0 0 1 +pinnumber=4 +T 2000 3000 5 8 1 1 0 6 1 +pinlabel=C2+ +} +P 2100 2200 2400 2200 1 0 1 +{ +T 2150 2250 5 8 1 1 0 0 1 +pinnumber=5 +T 2000 2200 5 8 1 1 0 6 1 +pinlabel=C1- +} +P 300 400 0 400 1 0 1 +{ +T 250 450 5 8 1 1 0 6 1 +pinnumber=6 +T 400 400 5 8 1 1 0 0 1 +pinlabel=V- +} +P 2100 1400 2400 1400 1 0 1 +{ +T 2150 1450 5 8 1 1 0 0 1 +pinnumber=7 +} +P 2100 600 2400 600 1 0 1 +{ +T 2150 650 5 8 1 1 0 0 1 +pinnumber=8 +} +B 300 0 1800 3400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 300 1800 1100 1800 3 0 0 0 -1 -1 +L 1100 1900 1100 1700 3 0 0 0 -1 -1 +L 1100 1700 1250 1800 3 0 0 0 -1 -1 +L 1100 1900 1250 1800 3 0 0 0 -1 -1 +V 1275 1800 26 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 1300 1800 2100 1800 3 0 0 0 -1 -1 +L 300 1400 1100 1400 3 0 0 0 -1 -1 +L 1100 1500 1100 1300 3 0 0 0 -1 -1 +L 1100 1300 1250 1400 3 0 0 0 -1 -1 +L 1100 1500 1250 1400 3 0 0 0 -1 -1 +V 1275 1400 26 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 1300 1400 2100 1400 3 0 0 0 -1 -1 +T 400 1900 9 8 1 0 0 0 1 +CMOS +T 1700 1900 9 8 1 0 0 0 1 +232 +L 2100 1000 1300 1000 3 0 0 0 -1 -1 +L 1300 1100 1300 900 3 0 0 0 -1 -1 +L 1300 900 1150 1000 3 0 0 0 -1 -1 +L 1300 1100 1150 1000 3 0 0 0 -1 -1 +V 1125 1000 26 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 1100 1000 300 1000 3 0 0 0 -1 -1 +L 2100 600 1300 600 3 0 0 0 -1 -1 +L 1300 700 1300 500 3 0 0 0 -1 -1 +L 1300 500 1150 600 3 0 0 0 -1 -1 +L 1300 700 1150 600 3 0 0 0 -1 -1 +V 1125 600 26 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 1100 600 300 600 3 0 0 0 -1 -1 +T 300 4400 9 10 0 0 0 0 1 +author=Darrell Harmon mail@dlharmon.com +T 300 4200 9 10 0 0 0 0 1 +dist-license=GPL +T 300 4000 9 10 0 0 0 0 1 +use-license=unlimited +T 300 3800 9 10 0 0 0 0 1 +tested=yes +T 300 3600 9 10 0 0 0 0 1 +style=compact diff --git a/P8000_WDC_Emulator/P8000_WDC_Emulator/Hardware/osc.sym b/P8000_WDC_Emulator/P8000_WDC_Emulator/Hardware/osc.sym new file mode 100755 index 0000000..7ef963a --- /dev/null +++ b/P8000_WDC_Emulator/P8000_WDC_Emulator/Hardware/osc.sym @@ -0,0 +1,68 @@ +v 20080127 1 +P 2000 900 1700 900 1 0 0 +{ +T 1800 950 5 8 1 1 0 0 1 +pinnumber=8 +T 1800 850 5 8 0 1 0 2 1 +pinseq=3 +T 1650 900 9 8 1 1 0 6 1 +pinlabel=Out +T 1650 900 5 8 0 1 0 8 1 +pintype=out +} +P 1000 0 1000 300 1 0 0 +{ +T 1050 200 5 8 1 1 0 2 1 +pinnumber=7 +T 950 200 5 8 0 1 0 8 1 +pinseq=2 +T 1000 350 9 8 1 1 0 3 1 +pinlabel=GND +T 1000 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 0 900 300 900 1 0 0 +{ +T 200 950 5 8 1 1 0 6 1 +pinnumber=14 +T 200 850 5 8 0 1 0 8 1 +pinseq=4 +T 350 900 9 8 1 1 0 0 1 +pinlabel=Vcc +T 350 900 5 8 0 1 0 2 1 +pintype=pwr +} +B 300 300 1400 900 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 1900 1300 8 10 1 1 0 6 1 +refdes=U? +T 300 1300 9 10 1 0 0 0 1 +OSC +T 300 1550 5 10 0 0 0 0 1 +device=OSC +T 300 1750 5 10 0 0 0 0 1 +footprint=OSC__Crystek_CCHD-950 +T 300 1950 5 10 0 0 0 0 1 +author=Stefan Salewski +T 300 2150 5 10 0 0 0 0 1 +documentation=http://www.crystekcrystals.com/crystal/clock/clock-complete.asp +T 300 2350 5 10 0 0 0 0 1 +description=Oscillator Crystek_CCHD-950 +T 300 2550 5 10 0 0 0 0 1 +numslots=0 +T 300 2750 5 10 0 0 0 0 1 +dist-license=GPL +T 300 2950 5 10 0 0 0 0 1 +use-license=unlimited +T 300 3150 5 10 0 0 0 0 1 +comment=generated with Python script tragesym +L 800 1000 900 1000 3 0 0 0 -1 -1 +L 900 1000 900 800 3 0 0 0 -1 -1 +L 900 800 1000 800 3 0 0 0 -1 -1 +L 1000 800 1000 1000 3 0 0 0 -1 -1 +L 1000 1000 1100 1000 3 0 0 0 -1 -1 +L 1100 1000 1100 800 3 0 0 0 -1 -1 +L 700 800 800 800 3 0 0 0 -1 -1 +L 800 800 800 1000 3 0 0 0 -1 -1 +L 1100 800 1200 800 3 0 0 0 -1 -1 +L 1200 800 1200 1000 3 0 0 0 -1 -1 +L 1200 1000 1300 1000 3 0 0 0 -1 -1 diff --git a/P8000_WDC_Emulator/P8000_WDC_Emulator/Hardware/rpack4-1.sym b/P8000_WDC_Emulator/P8000_WDC_Emulator/Hardware/rpack4-1.sym new file mode 100755 index 0000000..947463d --- /dev/null +++ b/P8000_WDC_Emulator/P8000_WDC_Emulator/Hardware/rpack4-1.sym @@ -0,0 +1,88 @@ +v 20091004 2 +P 0 1800 500 1800 1 0 0 +{ +T 405 1845 5 10 1 1 0 6 1 +pinnumber=1 +} +P 0 1300 500 1300 1 0 0 +{ +T 405 1345 5 10 1 1 0 6 1 +pinnumber=2 +} +P 0 800 500 800 1 0 0 +{ +T 405 845 5 10 1 1 0 6 1 +pinnumber=3 +} +P 0 300 500 300 1 0 0 +{ +T 405 345 5 10 1 1 0 6 1 +pinnumber=4 +} +P 2400 1800 1900 1800 1 0 0 +{ +T 1995 1845 5 10 1 1 0 0 1 +pinnumber=8 +} +P 2400 1300 1900 1300 1 0 0 +{ +T 1995 1345 5 10 1 1 0 0 1 +pinnumber=7 +} +P 2400 800 1900 800 1 0 0 +{ +T 1995 845 5 10 1 1 0 0 1 +pinnumber=6 +} +P 2400 300 1900 300 1 0 0 +{ +T 1995 345 5 10 1 1 0 0 1 +pinnumber=5 +} +T 95 3100 5 10 0 0 0 0 1 +device=rpack4 +T 95 2900 5 10 0 0 0 0 1 +footprint=0603_rpack4 +T 95 2700 5 10 0 0 0 0 1 +description=Four-in-one resistor network (isolated) +T 95 2500 5 10 0 0 0 0 1 +author=Vanessa Ezekowitz +L 500 1800 600 1800 3 0 0 0 -1 -1 +L 600 1800 700 2000 3 0 0 0 -1 -1 +L 700 2000 900 1600 3 0 0 0 -1 -1 +L 900 1600 1100 2000 3 0 0 0 -1 -1 +L 1100 2000 1300 1600 3 0 0 0 -1 -1 +L 1300 1600 1500 2000 3 0 0 0 -1 -1 +L 1500 2000 1700 1600 3 0 0 0 -1 -1 +L 1700 1600 1800 1800 3 0 0 0 -1 -1 +L 1800 1800 1900 1800 3 0 0 0 -1 -1 +L 500 1300 600 1300 3 0 0 0 -1 -1 +L 600 1300 700 1500 3 0 0 0 -1 -1 +L 700 1500 900 1100 3 0 0 0 -1 -1 +L 900 1100 1100 1500 3 0 0 0 -1 -1 +L 1100 1500 1300 1100 3 0 0 0 -1 -1 +L 1300 1100 1500 1500 3 0 0 0 -1 -1 +L 1500 1500 1700 1100 3 0 0 0 -1 -1 +L 1700 1100 1800 1300 3 0 0 0 -1 -1 +L 1800 1300 1900 1300 3 0 0 0 -1 -1 +L 500 800 600 800 3 0 0 0 -1 -1 +L 600 800 700 1000 3 0 0 0 -1 -1 +L 700 1000 900 600 3 0 0 0 -1 -1 +L 900 600 1100 1000 3 0 0 0 -1 -1 +L 1100 1000 1300 600 3 0 0 0 -1 -1 +L 1300 600 1500 1000 3 0 0 0 -1 -1 +L 1500 1000 1700 600 3 0 0 0 -1 -1 +L 1700 600 1800 800 3 0 0 0 -1 -1 +L 1800 800 1900 800 3 0 0 0 -1 -1 +L 500 300 600 300 3 0 0 0 -1 -1 +L 600 300 700 500 3 0 0 0 -1 -1 +L 700 500 900 100 3 0 0 0 -1 -1 +L 900 100 1100 500 3 0 0 0 -1 -1 +L 1100 500 1300 100 3 0 0 0 -1 -1 +L 1300 100 1500 500 3 0 0 0 -1 -1 +L 1500 500 1700 100 3 0 0 0 -1 -1 +L 1700 100 1800 300 3 0 0 0 -1 -1 +L 1800 300 1900 300 3 0 0 0 -1 -1 +B 500 0 1400 2100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 1595 2100 8 10 1 1 0 0 1 +refdes=RP?