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format the code using uncrustify 

migrate uart.[ch] to a BSD style license by reimplementing it
This commit is contained in:
Oliver Lehmann 2013-05-04 15:40:14 +00:00
parent 71a73da3a3
commit 33fd0a9dc5
17 changed files with 404 additions and 402 deletions
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225
P8000_WDC_Emulator/P8000_WDC_Emulator/uart.c
View File

@ -1,198 +1,145 @@
/* /*-
* Copyright (c) 2006-2011 by Roland Riegel <feedback@roland-riegel.de> * Copyright (c) 2013 Oliver Lehmann
* All rights reserved.
* *
* This file is free software; you can redistribute it and/or modify * Redistribution and use in source and binary forms, with or without
* it under the terms of the GNU General Public License version 2 as * modification, are permitted provided that the following conditions
* published by the Free Software Foundation. * are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer
* in this position and unchanged.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/*
* $Id: uart.c,v 1.6 2013/05/04 15:40:14 olivleh1 Exp $
*/ */
#include <stdio.h> #include <stdio.h>
#include <avr/interrupt.h> #include <avr/interrupt.h>
#include <avr/io.h> #include <avr/io.h>
#include <avr/pgmspace.h>
#include <avr/sfr_defs.h> #include <avr/sfr_defs.h>
#include <avr/sleep.h> #include <avr/sleep.h>
#include "uart.h" #include "uart.h"
#include "wdc_config.h" #include "wdc_config.h"
/* some mcus have multiple uarts */ /* Define baud rate */
#ifdef UDR0
#define UBRRH UBRR0H
#define UBRRL UBRR0L
#define UDR UDR0
#define UCSRA UCSR0A
#define UDRE UDRE0
#define RXC RXC0
#define UCSRB UCSR0B
#define RXEN RXEN0
#define TXEN TXEN0
#define RXCIE RXCIE0
#define UCSRC UCSR0C
#define URSEL
#define UCSZ0 UCSZ00
#define UCSZ1 UCSZ01
#define UCSRC_SELECT 0
#else
#define UCSRC_SELECT (1 << URSEL)
#endif
#ifndef USART_RXC_vect
#if defined(UART0_RX_vect)
#define USART_RXC_vect UART0_RX_vect
#elif defined(UART_RX_vect)
#define USART_RXC_vect UART_RX_vect
#elif defined(USART0_RX_vect)
#define USART_RXC_vect USART0_RX_vect
#elif defined(USART_RX_vect)
#define USART_RXC_vect USART_RX_vect
#elif defined(USART0_RXC_vect)
#define USART_RXC_vect USART0_RXC_vect
#elif defined(USART_RXC_vect)
#define USART_RXC_vect USART_RXC_vect
#else
#error "Uart receive complete interrupt not defined!"
#endif
#endif
#define BAUD 9600UL #define BAUD 9600UL
#define UBRRVAL (F_CPU/(BAUD*16)-1) #define UBBR_VALUE (( F_CPU / ( BAUD * 16 )) - 1 )
#define USE_SLEEP 1
void uart_init()
void uart_init ()
{ {
/* set baud rate */ /* Set baud rate */
UBRRH = UBRRVAL >> 8; UBRR0H = (uint8_t)( UBBR_VALUE >> 8 );
UBRRL = UBRRVAL & 0xff; UBRR0L = (uint8_t)UBBR_VALUE;
/* set frame format: 8 bit, no parity, 1 bit */ /* Set frame format to 8 data bits, no parity, 1 stop bit */
UCSRC = UCSRC_SELECT | (1 << UCSZ1) | (1 << UCSZ0); UCSR0C = ( 0 << USBS0 ) | ( 1 << UCSZ01 ) | ( 1 << UCSZ00 );
/* enable serial receiver and transmitter */ /* Enable receiver and transmitter */
#if !USE_SLEEP UCSR0B = ( 1 << RXEN0 ) | ( 1 << TXEN0 );
UCSRB = (1 << RXEN) | (1 << TXEN);
#else
UCSRB = (1 << RXEN) | (1 << TXEN) | (1 << RXCIE);
#endif
} }
void uart_putc(uint8_t c) void uart_putc ( uint8_t data )
{ {
if(c == '\n') /* Wait if a byte is being transmitted */
uart_putc('\r'); while ( ( UCSR0A & ( 1 << UDRE0 ) ) == 0 ) {}
/* wait until transmit buffer is empty */ /* Transmit data */
while(!(UCSRA & (1 << UDRE))); UDR0 = data;
/* send next byte */
UDR = c;
} }
void uart_putc_hex(uint8_t b) void uart_putc_hex ( uint8_t b )
{ {
/* upper nibble */ /* upper nibble */
if((b >> 4) < 0x0a) if ( ( b >> 4 ) < 0x0a ) {
uart_putc((b >> 4) + '0'); uart_putc ( ( b >> 4 ) + '0' );
else } else {
uart_putc((b >> 4) - 0x0a + 'a'); uart_putc ( ( b >> 4 ) - 0x0a + 'a' );
}
/* lower nibble */ /* lower nibble */
if((b & 0x0f) < 0x0a) if ( ( b & 0x0f ) < 0x0a ) {
uart_putc((b & 0x0f) + '0'); uart_putc ( ( b & 0x0f ) + '0' );
else } else {
uart_putc((b & 0x0f) - 0x0a + 'a'); uart_putc ( ( b & 0x0f ) - 0x0a + 'a' );
}
} }
void uart_putw_hex(uint16_t w) void uart_putw_dec ( uint16_t w )
{
uart_putc_hex((uint8_t) (w >> 8));
uart_putc_hex((uint8_t) (w & 0xff));
}
void uart_putdw_hex(uint32_t dw)
{
uart_putw_hex((uint16_t) (dw >> 16));
uart_putw_hex((uint16_t) (dw & 0xffff));
}
void uart_putw_dec(uint16_t w)
{ {
uint16_t num = 10000; uint16_t num = 10000;
uint8_t started = 0; uint8_t started = 0;
while(num > 0) while ( num > 0 ) {
{
uint8_t b = w / num; uint8_t b = w / num;
if(b > 0 || started || num == 1)
{ if ( b > 0 || started || num == 1 ) {
uart_putc('0' + b); uart_putc ( '0' + b );
started = 1; started = 1;
} }
w -= b * num;
w -= b * num;
num /= 10; num /= 10;
} }
} }
void uart_putdw_dec(uint32_t dw) void uart_putdw_dec ( uint32_t dw )
{ {
uint32_t num = 1000000000; uint32_t num = 1000000000;
uint8_t started = 0; uint8_t started = 0;
while(num > 0) while ( num > 0 ) {
{
uint8_t b = dw / num; uint8_t b = dw / num;
if(b > 0 || started || num == 1)
{ if ( b > 0 || started || num == 1 ) {
uart_putc('0' + b); uart_putc ( '0' + b );
started = 1; started = 1;
} }
dw -= b * num;
dw -= b * num;
num /= 10; num /= 10;
} }
} }
void uart_puts(const char* str) void uart_put_nl ()
{ {
while(*str) uart_putc ( '\n' );
uart_putc(*str++); uart_putc ( '\r' );
} }
void uart_puts_p(PGM_P str) void uart_putstring ( PGM_P str, bool newline )
{ {
while(1) uint8_t i = 0;
{
uint8_t b = pgm_read_byte_near(str++);
if(!b)
break;
uart_putc(b); while ( 1 ) {
char c = pgm_read_byte ( &str[i] );
if ( c != '\0' ) {
uart_putc ( c );
i++;
} else {
break;
}
}
if ( newline ) {
uart_put_nl();
} }
} }
uint8_t uart_getc() EMPTY_INTERRUPT ( USART0_RX_vect )
{
uint8_t b;
/* wait until receive buffer is full */
#if USE_SLEEP
uint8_t sreg = SREG;
sei();
while(!(UCSRA & (1 << RXC)))
sleep_mode();
SREG = sreg;
#else
while(!(UCSRA & (1 << RXC)));
#endif
b = UDR;
if(b == '\r')
b = '\n';
return b;
}
EMPTY_INTERRUPT(USART_RXC_vect)

52
P8000_WDC_Emulator/P8000_WDC_Emulator/uart.h
View File

@ -1,15 +1,39 @@
/* /*-
* Copyright (c) 2006-2011 by Roland Riegel <feedback@roland-riegel.de> * Copyright (c) 2013 Oliver Lehmann
* All rights reserved.
* *
* This file is free software; you can redistribute it and/or modify * Redistribution and use in source and binary forms, with or without
* it under the terms of the GNU General Public License version 2 as * modification, are permitted provided that the following conditions
* published by the Free Software Foundation. * are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer
* in this position and unchanged.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/*
* $Id: uart.h,v 1.2 2013/05/04 15:40:14 olivleh1 Exp $
*/ */
#ifndef UART_H #ifndef UART_H
#define UART_H #define UART_H
#include <stdint.h> #include <stdint.h>
#include <stdbool.h>
#include <avr/pgmspace.h> #include <avr/pgmspace.h>
#ifdef __cplusplus #ifdef __cplusplus
@ -17,21 +41,19 @@ extern "C"
{ {
#endif #endif
void uart_init(); void uart_init ();
void uart_putc(uint8_t c); void uart_putc ( uint8_t c );
void uart_putc_hex(uint8_t b); void uart_putc_hex ( uint8_t b );
void uart_putw_hex(uint16_t w);
void uart_putdw_hex(uint32_t dw);
void uart_putw_dec(uint16_t w); void uart_putw_dec ( uint16_t w );
void uart_putdw_dec(uint32_t dw); void uart_putdw_dec ( uint32_t dw );
void uart_puts(const char* str); void uart_puts ( const char *str );
void uart_puts_p(PGM_P str); void uart_putstring ( PGM_P str, bool newline );
uint8_t uart_getc(); void uart_put_nl ();
#ifdef __cplusplus #ifdef __cplusplus
} }

9
P8000_WDC_Emulator/P8000_WDC_Emulator/wdc_avr.c
View File

@ -26,10 +26,9 @@
*/ */
/* /*
* $Id: wdc_avr.c,v 1.5 2013/04/20 23:22:47 olivleh1 Exp $ * $Id: wdc_avr.c,v 1.6 2013/05/04 15:40:14 olivleh1 Exp $
*/ */
#include <avr/io.h> #include <avr/io.h>
#include "wdc_config.h" #include "wdc_config.h"
#include "wdc_avr.h" #include "wdc_avr.h"
@ -37,7 +36,7 @@
#include "wdc_drv_pata.h" #include "wdc_drv_pata.h"
#include "wdc_if_disk.h" #include "wdc_if_disk.h"
void wdc_init_avr() void wdc_init_avr ()
{ {
/* configure the P8000 interface */ /* configure the P8000 interface */
configure_pin_status0(); configure_pin_status0();
@ -81,11 +80,12 @@ void wdc_init_avr()
ata_da2_disable(); ata_da2_disable();
} }
void wdc_get_sysconf() void wdc_get_sysconf ()
{ {
enable_sysconf(); enable_sysconf();
nop(); nop();
nop(); nop();
if ( jumper_pata_set() ) { if ( jumper_pata_set() ) {
drv_init = pata_init; drv_init = pata_init;
drv_read_block = pata_read_block; drv_read_block = pata_read_block;
@ -99,5 +99,6 @@ void wdc_get_sysconf()
drv_read_multiblock = mmc_read_multiblock; drv_read_multiblock = mmc_read_multiblock;
drv_write_multiblock = mmc_write_multiblock; drv_write_multiblock = mmc_write_multiblock;
} }
disable_sysconf(); disable_sysconf();
} }

53
P8000_WDC_Emulator/P8000_WDC_Emulator/wdc_avr.h
View File

@ -26,10 +26,9 @@
*/ */
/* /*
* $Id: wdc_avr.h,v 1.6 2013/04/21 20:19:41 olivleh1 Exp $ * $Id: wdc_avr.h,v 1.7 2013/05/04 15:40:14 olivleh1 Exp $
*/ */
#ifndef WDC_AVR_H_ #ifndef WDC_AVR_H_
#define WDC_AVR_H_ #define WDC_AVR_H_
@ -44,8 +43,8 @@
#define configure_pin_tr() DDR_INFO |= ( 1 << PIN_INFO_TR ) #define configure_pin_tr() DDR_INFO |= ( 1 << PIN_INFO_TR )
#define configure_pin_reset() DDR_INFO &= ~( 1 << PIN_INFO_RST ); PORT_INFO |= ( 1 << PIN_INFO_RST ) #define configure_pin_reset() DDR_INFO &= ~( 1 << PIN_INFO_RST ); PORT_INFO |= ( 1 << PIN_INFO_RST )
#define port_data_set(x) ( PORT_DATA = ( x ) ) #define port_data_set( x ) ( PORT_DATA = ( x ) )
#define port_info_set(x) ( PORT_INFO = ( x ) ) #define port_info_set( x ) ( PORT_INFO = ( x ) )
#define port_data_get() PIN_DATA #define port_data_get() PIN_DATA
#define port_info_get() PIN_INFO #define port_info_get() PIN_INFO
@ -65,19 +64,19 @@
#define disable_sysconf() PORT_ADRDEC &= ~( ( 1 << PIN_ADRDEC_ADDR0 ) | ( 1 << PIN_ADRDEC_ADDR1 ) | ( 1 << PIN_ADRDEC_ADDR2 ) ) #define disable_sysconf() PORT_ADRDEC &= ~( ( 1 << PIN_ADRDEC_ADDR0 ) | ( 1 << PIN_ADRDEC_ADDR1 ) | ( 1 << PIN_ADRDEC_ADDR2 ) )
/* functions dealing with the MMC interface */ /* functions dealing with the MMC interface */
#define configure_pin_miso() DDR_MMC &= ~ ( 1 << PIN_MMC_MISO ) #define configure_pin_miso() DDR_MMC &= ~( 1 << PIN_MMC_MISO )
#define configure_pin_sck() DDR_MMC |= ( 1 << PIN_MMC_SCK ) #define configure_pin_sck() DDR_MMC |= ( 1 << PIN_MMC_SCK )
#define configure_pin_mosi() DDR_MMC |= ( 1 << PIN_MMC_MOSI ) #define configure_pin_mosi() DDR_MMC |= ( 1 << PIN_MMC_MOSI )
#define configure_pin_mmc_cs() DDR_MMC |= ( 1 << PIN_MMC_CS ) #define configure_pin_mmc_cs() DDR_MMC |= ( 1 << PIN_MMC_CS )
#define disable_mmc() PORT_MMC |= (1<<PIN_MMC_CS); #define disable_mmc() PORT_MMC |= ( 1 << PIN_MMC_CS );
#define enable_mmc() PORT_MMC &=~(1<<PIN_MMC_CS); #define enable_mmc() PORT_MMC &= ~( 1 << PIN_MMC_CS );
/* functions dealing with the sysconf jumperpad */ /* functions dealing with the sysconf jumperpad */
#define jumper_pata_set() ~port_data_get() & (1<<PIN_DATA_D0) #define jumper_pata_set() ~port_data_get() & ( 1 << PIN_DATA_D0 )
#define jumper_nn2_set() ~port_data_get() & (1<<PIN_DATA_D1) #define jumper_nn2_set() ~port_data_get() & ( 1 << PIN_DATA_D1 )
#define jumper_nn3_set() ~port_data_get() & (1<<PIN_DATA_D2) #define jumper_nn3_set() ~port_data_get() & ( 1 << PIN_DATA_D2 )
#define jumper_nn4_set() ~port_data_get() & (1<<PIN_DATA_D3) #define jumper_nn4_set() ~port_data_get() & ( 1 << PIN_DATA_D3 )
/* functions dealing with the ATA interface */ /* functions dealing with the ATA interface */
#define configure_ata_wr() DDR_ATARDWR |= ( 1 << PIN_ATARDWR_WR ) #define configure_ata_wr() DDR_ATARDWR |= ( 1 << PIN_ATARDWR_WR )
@ -88,22 +87,22 @@
#define configure_ata_da1() DDR_ATADA |= ( 1 << PIN_ATADA_DA1 ) #define configure_ata_da1() DDR_ATADA |= ( 1 << PIN_ATADA_DA1 )
#define configure_ata_da2() DDR_ATADA |= ( 1 << PIN_ATADA_DA2 ) #define configure_ata_da2() DDR_ATADA |= ( 1 << PIN_ATADA_DA2 )
#define ata_wr_disable() PORT_ATARDWR |= (1<<PIN_ATARDWR_WR) #define ata_wr_disable() PORT_ATARDWR |= ( 1 << PIN_ATARDWR_WR )
#define ata_wr_enable() PORT_ATARDWR &= ~(1<<PIN_ATARDWR_WR) #define ata_wr_enable() PORT_ATARDWR &= ~( 1 << PIN_ATARDWR_WR )
#define ata_rd_disable() PORT_ATARDWR |= (1<<PIN_ATARDWR_RD) #define ata_rd_disable() PORT_ATARDWR |= ( 1 << PIN_ATARDWR_RD )
#define ata_rd_enable() PORT_ATARDWR &= ~(1<<PIN_ATARDWR_RD) #define ata_rd_enable() PORT_ATARDWR &= ~( 1 << PIN_ATARDWR_RD )
#define ata_cs0_disable() PORT_ATACS |= (1<<PIN_ATACS_CS0) #define ata_cs0_disable() PORT_ATACS |= ( 1 << PIN_ATACS_CS0 )
#define ata_cs0_enable() PORT_ATACS &= ~(1<<PIN_ATACS_CS0) #define ata_cs0_enable() PORT_ATACS &= ~( 1 << PIN_ATACS_CS0 )
#define ata_cs1_disable() PORT_ATACS |= (1<<PIN_ATACS_CS1) #define ata_cs1_disable() PORT_ATACS |= ( 1 << PIN_ATACS_CS1 )
#define ata_cs1_enable() PORT_ATACS &= ~(1<<PIN_ATACS_CS1) #define ata_cs1_enable() PORT_ATACS &= ~( 1 << PIN_ATACS_CS1 )
#define ata_da0_disable() PORT_ATADA |= (1<<PIN_ATADA_DA0) #define ata_da0_disable() PORT_ATADA |= ( 1 << PIN_ATADA_DA0 )
#define ata_da0_enable() PORT_ATADA &= ~(1<<PIN_ATADA_DA0) #define ata_da0_enable() PORT_ATADA &= ~( 1 << PIN_ATADA_DA0 )
#define ata_da1_disable() PORT_ATADA |= (1<<PIN_ATADA_DA1) #define ata_da1_disable() PORT_ATADA |= ( 1 << PIN_ATADA_DA1 )
#define ata_da1_enable() PORT_ATADA &= ~(1<<PIN_ATADA_DA1) #define ata_da1_enable() PORT_ATADA &= ~( 1 << PIN_ATADA_DA1 )
#define ata_da2_disable() PORT_ATADA |= (1<<PIN_ATADA_DA2) #define ata_da2_disable() PORT_ATADA |= ( 1 << PIN_ATADA_DA2 )
#define ata_da2_enable() PORT_ATADA &= ~(1<<PIN_ATADA_DA2) #define ata_da2_enable() PORT_ATADA &= ~( 1 << PIN_ATADA_DA2 )
extern void wdc_init_avr(); extern void wdc_init_avr ();
extern void wdc_get_sysconf(); extern void wdc_get_sysconf ();
#endif /* WDC_AVR_H_ */ #endif /* WDC_AVR_H_ */

5
P8000_WDC_Emulator/P8000_WDC_Emulator/wdc_config.h
View File

@ -26,10 +26,9 @@
*/ */
/* /*
* $Id: wdc_config.h,v 1.21 2013/04/20 23:22:47 olivleh1 Exp $ * $Id: wdc_config.h,v 1.22 2013/05/04 15:40:14 olivleh1 Exp $
*/ */
#ifndef CONFIG_H_ #ifndef CONFIG_H_
#define CONFIG_H_ #define CONFIG_H_
@ -124,6 +123,6 @@
#define DEBUG 1 #define DEBUG 1
#define nop() __asm__ __volatile__ ("nop" ::) #define nop() __asm__ __volatile__ ( "nop" ::)
#endif /* CONFIG_H_ */ #endif /* CONFIG_H_ */

4
P8000_WDC_Emulator/P8000_WDC_Emulator/wdc_drv_mmc.h
View File

@ -26,7 +26,7 @@
*/ */
/* /*
* $Id: wdc_drv_mmc.h,v 1.9 2013/04/20 23:22:47 olivleh1 Exp $ * $Id: wdc_drv_mmc.h,v 1.10 2013/05/04 15:40:14 olivleh1 Exp $
*/ */
#ifndef WDC_DRV_MMC_H_ #ifndef WDC_DRV_MMC_H_
@ -43,5 +43,3 @@ extern uint8_t mmc_write_multiblock ( uint32_t addr, uint8_t *buffer, uint8_t nu
#define MMC_BLOCKLEN 512 #define MMC_BLOCKLEN 512
#endif /* WDC_DRV_MMC_H_ */ #endif /* WDC_DRV_MMC_H_ */

2
P8000_WDC_Emulator/P8000_WDC_Emulator/wdc_drv_pata.h
View File

@ -26,7 +26,7 @@
*/ */
/* /*
* $Id: wdc_drv_pata.h,v 1.8 2013/04/20 23:22:47 olivleh1 Exp $ * $Id: wdc_drv_pata.h,v 1.9 2013/05/04 15:40:14 olivleh1 Exp $
*/ */
#ifndef WDC_DRV_PATA_H_ #ifndef WDC_DRV_PATA_H_

54
P8000_WDC_Emulator/P8000_WDC_Emulator/wdc_if_disk.c
View File

@ -26,7 +26,7 @@
*/ */
/* /*
* $Id: wdc_if_disk.c,v 1.14 2013/04/20 23:22:47 olivleh1 Exp $ * $Id: wdc_if_disk.c,v 1.15 2013/05/04 15:40:14 olivleh1 Exp $
*/ */
#include <stdint.h> #include <stdint.h>
@ -36,22 +36,22 @@
#include "uart.h" #include "uart.h"
#include "wdc_par.h" #include "wdc_par.h"
uint8_t wdc_init_disk() uint8_t wdc_init_disk ()
{ {
return (*drv_init)(); return ( *drv_init )();
} }
uint32_t wdc_sector2diskblock ( uint16_t req_cylinder, uint8_t req_head, uint8_t req_sector ) uint32_t wdc_sector2diskblock ( uint16_t req_cylinder, uint8_t req_head, uint8_t req_sector )
{ {
return ( ( req_cylinder * wdc_get_hdd_heads() * wdc_get_hdd_sectors() ) return ( req_cylinder * wdc_get_hdd_heads() * wdc_get_hdd_sectors() )
+ ( req_head * wdc_get_hdd_sectors() ) + ( req_head * wdc_get_hdd_sectors() )
+ ( req_sector - 1 ) ); + ( req_sector - 1 );
} }
uint32_t wdc_p8kblock2diskblock ( uint32_t blockno ) uint32_t wdc_p8kblock2diskblock ( uint32_t blockno )
{ {
return ( blockno return blockno
+ ( wdc_get_hdd_heads() * wdc_get_hdd_sectors() ) ); + ( wdc_get_hdd_heads() * wdc_get_hdd_sectors() );
} }
uint8_t wdc_write_sector ( uint32_t addr, uint8_t *sector ) uint8_t wdc_write_sector ( uint32_t addr, uint8_t *sector )
@ -59,15 +59,17 @@ uint8_t wdc_write_sector ( uint32_t addr, uint8_t *sector )
uint8_t errorcode; uint8_t errorcode;
errorcode = drv_write_block ( addr, sector ); errorcode = drv_write_block ( addr, sector );
if ( errorcode ) { if ( errorcode ) {
uart_puts_p ( PSTR ( " write error at address: " ) ); uart_putstring ( PSTR ( "ERROR: write error at address: " ), false );
uart_putdw_dec ( addr ); uart_putdw_dec ( addr );
uart_puts_p ( PSTR ( " / errorcode is: " ) ); uart_putstring ( PSTR ( " / errorcode is: " ), false );
uart_putc_hex ( errorcode ); uart_putc_hex ( errorcode );
uart_putc ( '\n' ); uart_put_nl();
return errorcode; return errorcode;
} else } else {
return 0; return 0;
}
} }
uint8_t wdc_read_sector ( uint32_t addr, uint8_t *sector ) uint8_t wdc_read_sector ( uint32_t addr, uint8_t *sector )
@ -75,15 +77,17 @@ uint8_t wdc_read_sector ( uint32_t addr, uint8_t *sector )
uint8_t errorcode; uint8_t errorcode;
errorcode = drv_read_block ( addr, sector ); errorcode = drv_read_block ( addr, sector );
if ( errorcode ) { if ( errorcode ) {
uart_puts_p ( PSTR ( " read error at address: " ) ); uart_putstring ( PSTR ( "ERROR: read error at address: " ), false );
uart_putdw_dec ( addr ); uart_putdw_dec ( addr );
uart_puts_p ( PSTR ( " / errorcode is: " ) ); uart_putstring ( PSTR ( " / errorcode is: " ), false );
uart_putc_hex ( errorcode ); uart_putc_hex ( errorcode );
uart_putc ( '\n' ); uart_put_nl();
return errorcode; return errorcode;
} else } else {
return 0; return 0;
}
} }
uint8_t wdc_read_multiblock ( uint32_t addr, uint8_t *sector, uint8_t numblocks ) uint8_t wdc_read_multiblock ( uint32_t addr, uint8_t *sector, uint8_t numblocks )
@ -91,15 +95,17 @@ uint8_t wdc_read_multiblock ( uint32_t addr, uint8_t *sector, uint8_t numblocks
uint8_t errorcode; uint8_t errorcode;
errorcode = drv_read_multiblock ( addr, sector, numblocks ); errorcode = drv_read_multiblock ( addr, sector, numblocks );
if ( errorcode ) { if ( errorcode ) {
uart_puts_p ( PSTR ( " read error at address: " ) ); uart_putstring ( PSTR ( "ERROR: read error at address: " ), false );
uart_putdw_dec ( addr ); uart_putdw_dec ( addr );
uart_puts_p ( PSTR ( " / errorcode is: " ) ); uart_putstring ( PSTR ( " / errorcode is: " ), false );
uart_putc_hex ( errorcode ); uart_putc_hex ( errorcode );
uart_putc ( '\n' ); uart_put_nl();
return errorcode; return errorcode;
} else } else {
return 0; return 0;
}
} }
uint8_t wdc_write_multiblock ( uint32_t addr, uint8_t *sector, uint8_t numblocks ) uint8_t wdc_write_multiblock ( uint32_t addr, uint8_t *sector, uint8_t numblocks )
@ -107,13 +113,15 @@ uint8_t wdc_write_multiblock ( uint32_t addr, uint8_t *sector, uint8_t numblocks
uint8_t errorcode; uint8_t errorcode;
errorcode = drv_write_multiblock ( addr, sector, numblocks ); errorcode = drv_write_multiblock ( addr, sector, numblocks );
if ( errorcode ) { if ( errorcode ) {
uart_puts_p ( PSTR ( " write error at address: " ) ); uart_putstring ( PSTR ( "ERROR: write error at address: " ), false );
uart_putdw_dec ( addr ); uart_putdw_dec ( addr );
uart_puts_p ( PSTR ( " / errorcode is: " ) ); uart_putstring ( PSTR ( " / errorcode is: " ), false );
uart_putc_hex ( errorcode ); uart_putc_hex ( errorcode );
uart_putc ( '\n' ); uart_put_nl();
return errorcode; return errorcode;
} else } else {
return 0; return 0;
}
} }

14
P8000_WDC_Emulator/P8000_WDC_Emulator/wdc_if_disk.h
View File

@ -26,7 +26,7 @@
*/ */
/* /*
* $Id: wdc_if_disk.h,v 1.9 2013/04/20 23:22:47 olivleh1 Exp $ * $Id: wdc_if_disk.h,v 1.10 2013/05/04 15:40:14 olivleh1 Exp $
*/ */
#ifndef WDC_IF_DISK_H_ #ifndef WDC_IF_DISK_H_
@ -34,7 +34,7 @@
#include <stdio.h> #include <stdio.h>
extern uint8_t wdc_init_disk(); extern uint8_t wdc_init_disk ();
extern uint32_t wdc_sector2diskblock ( uint16_t req_cylinder, uint8_t req_head, uint8_t req_sector ); extern uint32_t wdc_sector2diskblock ( uint16_t req_cylinder, uint8_t req_head, uint8_t req_sector );
extern uint32_t wdc_p8kblock2diskblock ( uint32_t blockno ); extern uint32_t wdc_p8kblock2diskblock ( uint32_t blockno );
extern uint8_t wdc_write_sector ( uint32_t addr, uint8_t *sector ); extern uint8_t wdc_write_sector ( uint32_t addr, uint8_t *sector );
@ -42,13 +42,13 @@ extern uint8_t wdc_read_sector ( uint32_t addr, uint8_t *sector );
extern uint8_t wdc_read_multiblock ( uint32_t addr, uint8_t *sector, uint8_t numblocks ); extern uint8_t wdc_read_multiblock ( uint32_t addr, uint8_t *sector, uint8_t numblocks );
extern uint8_t wdc_write_multiblock ( uint32_t addr, uint8_t *sector, uint8_t numblocks ); extern uint8_t wdc_write_multiblock ( uint32_t addr, uint8_t *sector, uint8_t numblocks );
typedef uint8_t (*t_drv_init) (); typedef uint8_t ( *t_drv_init )();
typedef uint8_t (*t_drv_read_block) ( uint32_t addr, uint8_t *buffer ); typedef uint8_t ( *t_drv_read_block )( uint32_t addr, uint8_t *buffer );
typedef uint8_t (*t_drv_write_block) ( uint32_t addr, uint8_t *buffer ); typedef uint8_t ( *t_drv_write_block )( uint32_t addr, uint8_t *buffer );
typedef uint8_t (*t_drv_read_multiblock) ( uint32_t addr, uint8_t *buffer, uint8_t numblocks ); typedef uint8_t ( *t_drv_read_multiblock )( uint32_t addr, uint8_t *buffer, uint8_t numblocks );
typedef uint8_t (*t_drv_write_multiblock) ( uint32_t addr, uint8_t *buffer, uint8_t numblocks ); typedef uint8_t ( *t_drv_write_multiblock )( uint32_t addr, uint8_t *buffer, uint8_t numblocks );
t_drv_init drv_init; t_drv_init drv_init;
t_drv_read_block drv_read_block; t_drv_read_block drv_read_block;

70
P8000_WDC_Emulator/P8000_WDC_Emulator/wdc_if_disk_perf.c
View File

@ -26,7 +26,7 @@
*/ */
/* /*
* $Id: wdc_if_disk_perf.c,v 1.11 2013/04/20 23:22:47 olivleh1 Exp $ * $Id: wdc_if_disk_perf.c,v 1.12 2013/05/04 15:40:15 olivleh1 Exp $
*/ */
#include <avr/io.h> #include <avr/io.h>
@ -45,9 +45,8 @@
#define BLOCKNO 300000 #define BLOCKNO 300000
volatile uint32_t overflow = 0; volatile uint32_t overflow = 0;
ISR ( TIMER0_OVF_vect ) ISR ( TIMER0_OVF_vect ) {
{ overflow++;
overflow ++;
} }
/* switched from local to global for keeping an eye on memory usage */ /* switched from local to global for keeping an eye on memory usage */
@ -61,23 +60,28 @@ void test_write4k ( uint8_t numblocks, uint8_t nr_of_tests )
uint32_t blockno = 0; uint32_t blockno = 0;
uint8_t i8, errorcode; uint8_t i8, errorcode;
uart_puts_p ( PSTR ( "Test Write 5000 512B-Blocks with Multiblock-Write (4KB Blocksize):" ) ); uart_putstring ( PSTR ( "Test Write 5000 512B-Blocks with Multiblock-Write (4KB Blocksize):" ) );
uart_putc ( '\n' ); uart_putc ( '\n' );
memset ( &data_buffer[0], 0xCC, WDC_BLOCKLEN * numblocks ); memset ( &data_buffer[0], 0xCC, WDC_BLOCKLEN * numblocks );
for ( i8 = 0; i8 < nr_of_tests; i8++ ) { for ( i8 = 0; i8 < nr_of_tests; i8++ ) {
blockno = BLOCKNO; blockno = BLOCKNO;
for ( starttime = overflow; blockno < ( ( uint32_t ) BLOCKNO + 5000 ); blockno += numblocks ) {
for ( starttime = overflow; blockno < ( (uint32_t)BLOCKNO + 5000 ); blockno += numblocks ) {
errorcode = wdc_write_multiblock ( blockno, data_buffer, numblocks ); errorcode = wdc_write_multiblock ( blockno, data_buffer, numblocks );
if ( errorcode ) { if ( errorcode ) {
break; break;
} }
} }
if ( errorcode )
if ( errorcode ) {
break; break;
}
uart_putdw_dec ( overflow - starttime ); uart_putdw_dec ( overflow - starttime );
uart_putc ( '\n' ); uart_putc ( '\n' );
} }
} }
void test_read4k ( uint8_t numblocks, uint8_t nr_of_tests ) void test_read4k ( uint8_t numblocks, uint8_t nr_of_tests )
@ -86,23 +90,27 @@ void test_read4k ( uint8_t numblocks, uint8_t nr_of_tests )
uint32_t blockno = 0; uint32_t blockno = 0;
uint8_t i8, errorcode; uint8_t i8, errorcode;
uart_puts_p ( PSTR ( "Test Read 5000 512B-Blocks with Multiblock-Read (4KB Blocksize):" ) ); uart_putstring ( PSTR ( "Test Read 5000 512B-Blocks with Multiblock-Read (4KB Blocksize):" ) );
uart_putc ( '\n' ); uart_putc ( '\n' );
for ( i8 = 0; i8 < nr_of_tests; i8++ ) { for ( i8 = 0; i8 < nr_of_tests; i8++ ) {
blockno = BLOCKNO; blockno = BLOCKNO;
for ( starttime = overflow; blockno < ( ( uint32_t ) BLOCKNO + 5000 ); blockno += numblocks ) {
for ( starttime = overflow; blockno < ( (uint32_t)BLOCKNO + 5000 ); blockno += numblocks ) {
errorcode = wdc_read_multiblock ( blockno, data_buffer, numblocks ); errorcode = wdc_read_multiblock ( blockno, data_buffer, numblocks );
if ( errorcode ) { if ( errorcode ) {
break; break;
} }
} }
if ( errorcode )
if ( errorcode ) {
break; break;
}
uart_putdw_dec ( overflow - starttime ); uart_putdw_dec ( overflow - starttime );
uart_putc ( '\n' ); uart_putc ( '\n' );
} }
} }
void test_write512 ( uint8_t numblocks, uint8_t nr_of_tests ) void test_write512 ( uint8_t numblocks, uint8_t nr_of_tests )
@ -111,23 +119,28 @@ void test_write512 ( uint8_t numblocks, uint8_t nr_of_tests )
uint32_t blockno = 0; uint32_t blockno = 0;
uint8_t i8, errorcode; uint8_t i8, errorcode;
uart_puts_p ( PSTR ( "Test Write 5000 512B-Blocks with Singleblock-Write (512B Blocksize):" ) ); uart_putstring ( PSTR ( "Test Write 5000 512B-Blocks with Singleblock-Write (512B Blocksize):" ) );
uart_putc ( '\n' ); uart_putc ( '\n' );
memset ( &data_buffer[0], 0xEF, WDC_BLOCKLEN * numblocks ); memset ( &data_buffer[0], 0xEF, WDC_BLOCKLEN * numblocks );
for ( i8 = 0; i8 < nr_of_tests; i8++ ) { for ( i8 = 0; i8 < nr_of_tests; i8++ ) {
blockno = BLOCKNO; blockno = BLOCKNO;
for ( starttime = overflow; blockno < ( ( uint32_t ) BLOCKNO + 5000 ); blockno++ ) {
for ( starttime = overflow; blockno < ( (uint32_t)BLOCKNO + 5000 ); blockno++ ) {
errorcode = wdc_write_sector ( blockno, data_buffer ); errorcode = wdc_write_sector ( blockno, data_buffer );
if ( errorcode ) { if ( errorcode ) {
break; break;
} }
} }
if ( errorcode )
if ( errorcode ) {
break; break;
}
uart_putdw_dec ( overflow - starttime ); uart_putdw_dec ( overflow - starttime );
uart_putc ( '\n' ); uart_putc ( '\n' );
} }
} }
void test_read512 ( uint8_t numblocks, uint8_t nr_of_tests ) void test_read512 ( uint8_t numblocks, uint8_t nr_of_tests )
@ -136,26 +149,30 @@ void test_read512 ( uint8_t numblocks, uint8_t nr_of_tests )
uint32_t blockno = 0; uint32_t blockno = 0;
uint8_t i8, errorcode; uint8_t i8, errorcode;
uart_puts_p ( PSTR ( "Test Read 5000 512B-Blocks with Singleblock-Read (512B Blocksize):" ) ); uart_putstring ( PSTR ( "Test Read 5000 512B-Blocks with Singleblock-Read (512B Blocksize):" ) );
uart_putc ( '\n' ); uart_putc ( '\n' );
for ( i8 = 0; i8 < nr_of_tests; i8++ ) { for ( i8 = 0; i8 < nr_of_tests; i8++ ) {
blockno = BLOCKNO; blockno = BLOCKNO;
for ( starttime = overflow; blockno < ( ( uint32_t ) BLOCKNO + 5000 ); blockno++ ) {
for ( starttime = overflow; blockno < ( (uint32_t)BLOCKNO + 5000 ); blockno++ ) {
errorcode = wdc_read_sector ( blockno, data_buffer ); errorcode = wdc_read_sector ( blockno, data_buffer );
if ( errorcode ) { if ( errorcode ) {
break; break;
} }
} }
if ( errorcode )
if ( errorcode ) {
break; break;
}
uart_putdw_dec ( overflow - starttime ); uart_putdw_dec ( overflow - starttime );
uart_putc ( '\n' ); uart_putc ( '\n' );
} }
} }
void measure_performance() void measure_performance ()
{ {
uint8_t numblocks = 4; uint8_t numblocks = 4;
uint8_t nr_of_tests = 2; uint8_t nr_of_tests = 2;
@ -164,12 +181,10 @@ void measure_performance()
TIMSK0 |= ( 0x01 << TOIE0 ); TIMSK0 |= ( 0x01 << TOIE0 );
TCCR0B = ( 1 << CS01 ); /* Prescaler 8 */ TCCR0B = ( 1 << CS01 ); /* Prescaler 8 */
TCNT0 = 0x00; TCNT0 = 0x00;
uart_putstring ( PSTR ( "Performance Measurement. Displayed are the Timer-Overflows." ) );
uart_puts_p ( PSTR ( "Performance Measurement. Displayed are the Timer-Overflows." ) );
uart_putc ( '\n' ); uart_putc ( '\n' );
uart_puts_p ( PSTR ( "Timer is initialized with a Prescaler 8" ) ); uart_putstring ( PSTR ( "Timer is initialized with a Prescaler 8" ) );
uart_putc ( '\n' ); uart_putc ( '\n' );
test_write512 ( numblocks, nr_of_tests ); test_write512 ( numblocks, nr_of_tests );
test_read512 ( numblocks, nr_of_tests ); test_read512 ( numblocks, nr_of_tests );
test_write512 ( numblocks, nr_of_tests ); test_write512 ( numblocks, nr_of_tests );
@ -183,11 +198,10 @@ void measure_performance()
test_read512 ( numblocks, nr_of_tests ); test_read512 ( numblocks, nr_of_tests );
test_write4k ( numblocks, nr_of_tests ); test_write4k ( numblocks, nr_of_tests );
test_write512 ( numblocks, nr_of_tests ); test_write512 ( numblocks, nr_of_tests );
uart_putstring ( PSTR ( "End" ) );
uart_puts_p ( PSTR ( "End" ) );
uart_putc ( '\n' ); uart_putc ( '\n' );
while ( 1 ); while ( 1 ) {}
} }
#endif #endif

35
P8000_WDC_Emulator/P8000_WDC_Emulator/wdc_if_p8000.c
View File

@ -26,7 +26,7 @@
*/ */
/* /*
* $Id: wdc_if_p8000.c,v 1.15 2013/04/23 20:08:41 olivleh1 Exp $ * $Id: wdc_if_p8000.c,v 1.16 2013/05/04 15:40:15 olivleh1 Exp $
*/ */
#include "wdc_config.h" #include "wdc_config.h"
@ -36,14 +36,13 @@
#include "wdc_if_p8000.h" #include "wdc_if_p8000.h"
#include "wdc_par.h" #include "wdc_par.h"
void wdc_wait_for_reset() void wdc_wait_for_reset ()
{ {
while ( isset_info_reset() ) { while ( isset_info_reset() ) {
port_data_set ( DATA_CLEAR ); port_data_set ( DATA_CLEAR );
port_info_set ( INFO_CLEAR ); port_info_set ( INFO_CLEAR );
wdc_set_initialized ( 1 ); wdc_set_initialized ( 1 );
} }
} }
uint8_t wdc_read_data_from_p8k ( uint8_t *buffer, uint16_t count, uint8_t wdc_status ) uint8_t wdc_read_data_from_p8k ( uint8_t *buffer, uint16_t count, uint8_t wdc_status )
@ -55,16 +54,19 @@ uint8_t wdc_read_data_from_p8k ( uint8_t *buffer, uint16_t count, uint8_t wdc_st
configure_port_data_read(); configure_port_data_read();
datacnt = 0; datacnt = 0;
port_info_set ( wdc_status ); port_info_set ( wdc_status );
while ( !isset_info_te() )
if ( isset_info_reset() ) while ( !isset_info_te() ) {
if ( isset_info_reset() ) {
return 0; return 0;
while ( !isset_info_wdardy() ); }
}
while ( !isset_info_wdardy() ) {}
do { do {
enable_p8000com(); /* this also generates /ASTB in the moment /WDARDY gets low with a 7403 */ enable_p8000com(); /* this also generates /ASTB in the moment /WDARDY gets low with a 7403 */
while ( isset_info_wdardy() ); while ( isset_info_wdardy() ) {}
*buffer++ = port_data_get(); *buffer++ = port_data_get();
disable_p8000com(); /* this additionally brings /ASTB to high */ disable_p8000com(); /* this additionally brings /ASTB to high */
while ( !isset_info_wdardy() ); while ( !isset_info_wdardy() ) {}
datacnt++; datacnt++;
} while ( datacnt < count ); } while ( datacnt < count );
port_info_set ( INFO_CLEAR ); port_info_set ( INFO_CLEAR );
@ -79,24 +81,25 @@ void wdc_write_data_to_p8k ( uint8_t *buffer, uint16_t count, uint8_t wdc_status
_delay_us ( DELAY_PIO_US ); _delay_us ( DELAY_PIO_US );
port_info_set ( INFO_TR | wdc_status ); port_info_set ( INFO_TR | wdc_status );
while ( isset_info_te() ); while ( isset_info_te() ) {}
configure_port_data_write(); configure_port_data_write();
while ( !isset_info_wdardy() ); while ( !isset_info_wdardy() ) {}
do { do {
enable_p8000com(); /* this also generates /ASTB in the moment /WDARDY gets low with a 7403 */ enable_p8000com(); /* this also generates /ASTB in the moment /WDARDY gets low with a 7403 */
while ( isset_info_wdardy() ); while ( isset_info_wdardy() ) {}
port_data_set ( *buffer++ ); port_data_set ( *buffer++ );
disable_p8000com(); /* this additionally brings /ASTB to high */ disable_p8000com(); /* this additionally brings /ASTB to high */
while ( !isset_info_wdardy() ); while ( !isset_info_wdardy() ) {}
datacnt++; datacnt++;
} while ( datacnt < count ); } while ( datacnt < count );
while ( isset_info_wdardy() );
while ( isset_info_wdardy() ) {}
enable_p8000com(); enable_p8000com();
nop(); nop();
disable_p8000com(); disable_p8000com();
configure_port_data_read(); configure_port_data_read();
while ( !isset_info_wdardy() ); while ( !isset_info_wdardy() ) {}
port_info_set ( INFO_CLEAR ); port_info_set ( INFO_CLEAR );
} }
@ -124,7 +127,7 @@ void wdc_send_data ( uint8_t *buffer, uint16_t count )
); );
} }
void wdc_send_error() void wdc_send_error ()
{ {
wdc_send_errorcode ( 0x01 ); wdc_send_errorcode ( 0x01 );
} }

24
P8000_WDC_Emulator/P8000_WDC_Emulator/wdc_if_p8000.h
View File

@ -26,7 +26,7 @@
*/ */
/* /*
* $Id: wdc_if_p8000.h,v 1.12 2013/04/20 23:22:47 olivleh1 Exp $ * $Id: wdc_if_p8000.h,v 1.13 2013/05/04 15:40:15 olivleh1 Exp $
*/ */
#ifndef WDC_IF_P8000_H_ #ifndef WDC_IF_P8000_H_
@ -35,26 +35,26 @@
#define DELAY_PIO_US 550 #define DELAY_PIO_US 550
/* input pin handling */ /* input pin handling */
#define isset_info_reset() ((PIN_INFO) & (1 << PIN_INFO_RST)) #define isset_info_reset() (( PIN_INFO ) & ( 1 << PIN_INFO_RST ))
#define isset_info_te() ((PIN_INFO) & (1 << PIN_INFO_TE)) #define isset_info_te() (( PIN_INFO ) & ( 1 << PIN_INFO_TE ))
#define isset_info_wdardy() ((PIN_INFO) & (1 << PIN_INFO_WDARDY)) #define isset_info_wdardy() (( PIN_INFO ) & ( 1 << PIN_INFO_WDARDY ))
/* output pin handling */ /* output pin handling */
#define DATA_CLEAR 0x00 #define DATA_CLEAR 0x00
#define INFO_CLEAR 0x00 #define INFO_CLEAR 0x00
#define INFO_STAT_GCMD ((1 << PIN_INFO_STATUS0) ) /* 0x01 */ #define INFO_STAT_GCMD (( 1 << PIN_INFO_STATUS0 ) ) /* 0x01 */
#define INFO_STAT_RDATA ( (1 << PIN_INFO_STATUS1) ) /* 0x02 */ #define INFO_STAT_RDATA ( ( 1 << PIN_INFO_STATUS1 ) ) /* 0x02 */
#define INFO_STAT_WDATA ((1 << PIN_INFO_STATUS0) | (1 << PIN_INFO_STATUS1) ) /* 0x03 */ #define INFO_STAT_WDATA (( 1 << PIN_INFO_STATUS0 ) | ( 1 << PIN_INFO_STATUS1 ) ) /* 0x03 */
#define _INFO_STAT_CRCERR ( (1 << PIN_INFO_STATUS1) | (1 << PIN_INFO_STATUS2)) /* 0x06 */ #define _INFO_STAT_CRCERR ( ( 1 << PIN_INFO_STATUS1 ) | ( 1 << PIN_INFO_STATUS2 )) /* 0x06 */
#define INFO_STAT_ERROR ((1 << PIN_INFO_STATUS0) | (1 << PIN_INFO_STATUS1) | (1 << PIN_INFO_STATUS2)) /* 0x07 */ #define INFO_STAT_ERROR (( 1 << PIN_INFO_STATUS0 ) | ( 1 << PIN_INFO_STATUS1 ) | ( 1 << PIN_INFO_STATUS2 )) /* 0x07 */
#define INFO_TR (1 << PIN_INFO_TR) /* 0x40 */ #define INFO_TR ( 1 << PIN_INFO_TR ) /* 0x40 */
extern void wdc_wait_for_reset(); extern void wdc_wait_for_reset ();
extern uint8_t wdc_receive_cmd ( uint8_t *buffer, uint16_t count ); extern uint8_t wdc_receive_cmd ( uint8_t *buffer, uint16_t count );
extern void wdc_receive_data ( uint8_t *buffer, uint16_t count ); extern void wdc_receive_data ( uint8_t *buffer, uint16_t count );
extern void wdc_send_data ( uint8_t *buffer, uint16_t count ); extern void wdc_send_data ( uint8_t *buffer, uint16_t count );
extern void wdc_send_error(); extern void wdc_send_error ();
extern void wdc_send_errorcode ( uint8_t error ); extern void wdc_send_errorcode ( uint8_t error );
#endif /* WDC_IF_P8000_H_ */ #endif /* WDC_IF_P8000_H_ */

5
P8000_WDC_Emulator/P8000_WDC_Emulator/wdc_main.h
View File

@ -26,10 +26,9 @@
*/ */
/* /*
* $Id: wdc_main.h,v 1.13 2013/04/20 23:22:47 olivleh1 Exp $ * $Id: wdc_main.h,v 1.14 2013/05/04 15:40:15 olivleh1 Exp $
*/ */
#ifndef MAIN_H_ #ifndef MAIN_H_
#define MAIN_H_ #define MAIN_H_
@ -57,7 +56,7 @@
#define ___CMD_WRRDBTT_SECTOR 0x92 /* write and reread sector taking BTT into account */ #define ___CMD_WRRDBTT_SECTOR 0x92 /* write and reread sector taking BTT into account */
#define ___CMD_CP_BLOCK 0xa1 /* copy block from drive 1 to drive 0 */ #define ___CMD_CP_BLOCK 0xa1 /* copy block from drive 1 to drive 0 */
#define ___CMD_WRRD_BLOCK 0xa2 /* write and reread block */ #define ___CMD_WRRD_BLOCK 0xa2 /* write and reread block */
#define CMD_ST_PARBTT 0xc2 /* store PAR and BTT on hard disk */ #define CMD_ST_PARBTT 0xc2 /* store Parameter block and BTT on hard disk */
#define ERR_STANDARD 0x01 #define ERR_STANDARD 0x01
#define ERR_SECT_N_ON_SURFACE 0x0A #define ERR_SECT_N_ON_SURFACE 0x0A

82
P8000_WDC_Emulator/P8000_WDC_Emulator/wdc_par.c
View File

@ -26,7 +26,7 @@
*/ */
/* /*
* $Id: wdc_par.c,v 1.8 2013/04/21 00:40:52 olivleh1 Exp $ * $Id: wdc_par.c,v 1.9 2013/05/04 15:40:15 olivleh1 Exp $
*/ */
#include <avr/pgmspace.h> #include <avr/pgmspace.h>
@ -75,7 +75,9 @@
uint8_t par_table[512]; uint8_t par_table[512];
const uint8_t const uint8_t
par_tab_new_dsk[128] = {'W', 'D', 'C', '_', '4', '.', '2', 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, par_tab_new_dsk[128] =
{
'W', 'D', 'C', '_', '4', '.', '2', 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81,
0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x64, 0x00, 0x02, 0x12, 0x64, 0x00, 0x01, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x64, 0x00, 0x02, 0x12, 0x64, 0x00, 0x01, 0x81, 0x81,
0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, /* init with sa.format ends here */ 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, /* init with sa.format ends here */
/* to be initiated by controller starts here */ 0xEB, 0x0D, 0x00, 0x00, 0x41, 0x00, /* to be initiated by controller starts here */ 0xEB, 0x0D, 0x00, 0x00, 0x41, 0x00,
@ -84,10 +86,12 @@ par_tab_new_dsk[128] = {'W', 'D', 'C', '_', '4', '.', '2', 0x81, 0x81, 0x
0x00, 0x81, 0x00, 0x80, 0xfe, 0x00, 0x00, 0x00, 0x01, 0x81, 0x81, 0x73, 0x00, 0x12, 0x81, 0x01, 0x00, 0x81, 0x00, 0x80, 0xfe, 0x00, 0x00, 0x00, 0x01, 0x81, 0x81, 0x73, 0x00, 0x12, 0x81, 0x01,
0x00, 0x02, 0x00, 0x00, 0x81, 0x81, 0x81, 0x00, 0x41, 0xd7, 0x28, 0x81, 0x81, 0x81, 0x81, 0x81, 0x00, 0x02, 0x00, 0x00, 0x81, 0x81, 0x81, 0x00, 0x41, 0xd7, 0x28, 0x81, 0x81, 0x81, 0x81, 0x81,
0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81,
}; };
const uint8_t const uint8_t
par_tab_no_dsk[128] = {'W', 'D', 'C', '_', '4', '.', '2', 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, par_tab_no_dsk[128] =
{
'W', 'D', 'C', '_', '4', '.', '2', 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81,
0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x64, 0x00, 0x02, 0x12, 0x64, 0x00, 0x01, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x64, 0x00, 0x02, 0x12, 0x64, 0x00, 0x01, 0x81, 0x81,
0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, /* init with sa.format ends here */ 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, /* init with sa.format ends here */
/* to be initiated by controller starts here */ 0x81, 0x81, 0x81, 0x81, 0x40, 0x00, /* to be initiated by controller starts here */ 0x81, 0x81, 0x81, 0x81, 0x40, 0x00,
@ -96,7 +100,7 @@ par_tab_no_dsk[128] = {'W', 'D', 'C', '_', '4', '.', '2', 0x81, 0x81, 0x
0x00, 0x81, 0x00, 0x80, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x33, 0x00, 0x12, 0x81, 0x00, 0x00, 0x81, 0x00, 0x80, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x33, 0x00, 0x12, 0x81, 0x00,
0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x00, 0x40, 0xd7, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x00, 0x40, 0xd7, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81,
0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81,
}; };
uint8_t valid_disk = 1; uint8_t valid_disk = 1;
uint8_t initialized; uint8_t initialized;
@ -117,7 +121,6 @@ void wdc_write_par_table ( uint8_t *buffer, uint16_t count )
} while ( count > 0 ); } while ( count > 0 );
} }
void wdc_read_wdc_par ( uint8_t *buffer, uint16_t count ) void wdc_read_wdc_par ( uint8_t *buffer, uint16_t count )
{ {
do { do {
@ -134,11 +137,14 @@ void wdc_write_wdc_par ( uint8_t *buffer, uint16_t count )
} while ( count > 0 ); } while ( count > 0 );
} }
void wdc_del_wdc_btt() void wdc_del_wdc_btt ()
{ {
uint8_t i; uint8_t i;
for ( i = 0; i < 125; i++ )
for ( i = 0; i < 125; i++ ) {
par_table[i + POS_PAR_WDC_BTT] = 0x00; par_table[i + POS_PAR_WDC_BTT] = 0x00;
}
par_table[122 + POS_PAR_WDC_BTT] = 0xff; par_table[122 + POS_PAR_WDC_BTT] = 0xff;
} }
@ -158,14 +164,14 @@ void wdc_write_wdc_btt ( uint8_t *buffer, uint16_t count )
} while ( count > 0 ); } while ( count > 0 );
} }
uint16_t wdc_get_btt_count() uint16_t wdc_get_btt_count ()
{ {
return ( ( par_table[0 + POS_PAR_WDC_BTT] | ( par_table[1 + POS_PAR_WDC_BTT] << 8 ) ) ); return par_table[0 + POS_PAR_WDC_BTT] | ( par_table[1 + POS_PAR_WDC_BTT] << 8 );
} }
void wdc_set_btt_count ( uint16_t btt_count ) void wdc_set_btt_count ( uint16_t btt_count )
{ {
par_table[0 + POS_PAR_WDC_BTT] = ( uint8_t ) btt_count; par_table[0 + POS_PAR_WDC_BTT] = (uint8_t)btt_count;
par_table[1 + POS_PAR_WDC_BTT] = ( btt_count >> 8 ); par_table[1 + POS_PAR_WDC_BTT] = ( btt_count >> 8 );
} }
@ -178,46 +184,49 @@ uint8_t wdc_add_btt_entry ( uint16_t cylinder, uint8_t head )
/* storing the amount of bytes for the BTT */ /* storing the amount of bytes for the BTT */
par_table[btt_count + 2 + POS_PAR_WDC_BTT] = ( cylinder >> 8 ); par_table[btt_count + 2 + POS_PAR_WDC_BTT] = ( cylinder >> 8 );
btt_count++; btt_count++;
par_table[btt_count + 2 + POS_PAR_WDC_BTT] = ( uint8_t ) cylinder; par_table[btt_count + 2 + POS_PAR_WDC_BTT] = (uint8_t)cylinder;
btt_count++; btt_count++;
par_table[btt_count + 2 + POS_PAR_WDC_BTT] = ( uint8_t ) head; par_table[btt_count + 2 + POS_PAR_WDC_BTT] = (uint8_t)head;
btt_count++; btt_count++;
wdc_set_btt_count ( btt_count ); wdc_set_btt_count ( btt_count );
return ( 0 ); return 0;
} else { }else {
return ( ERR_BTT_FULL ); return ERR_BTT_FULL;
} }
} }
uint8_t wdc_get_hdd_sectors() uint8_t wdc_get_hdd_sectors ()
{ {
return ( par_table[18 + POS_PAR_WDC_PAR] ); return par_table[18 + POS_PAR_WDC_PAR];
} }
uint8_t wdc_get_hdd_heads() uint8_t wdc_get_hdd_heads ()
{ {
return ( par_table[17 + POS_PAR_WDC_PAR] ); return par_table[17 + POS_PAR_WDC_PAR];
}
uint16_t wdc_get_hdd_cylinder()
{
return ( ( par_table[16 + POS_PAR_WDC_PAR] << 8 ) | par_table[15 + POS_PAR_WDC_PAR] );
} }
void wdc_set_disk_invalid() uint16_t wdc_get_hdd_cylinder ()
{
return ( par_table[16 + POS_PAR_WDC_PAR] << 8 ) | par_table[15 + POS_PAR_WDC_PAR];
}
void wdc_set_disk_invalid ()
{ {
uint8_t i; uint8_t i;
valid_disk = 0; valid_disk = 0;
for ( i = 0; i < 128; i++ )
for ( i = 0; i < 128; i++ ) {
par_table[i] = par_tab_new_dsk[i]; par_table[i] = par_tab_new_dsk[i];
}
} }
void wdc_set_disk_valid() void wdc_set_disk_valid ()
{ {
uint32_t blocks; uint32_t blocks;
uint16_t zw0, zw1; uint16_t zw0, zw1;
blocks = (uint32_t)wdc_get_hdd_sectors() * (uint32_t)wdc_get_hdd_heads() * (uint32_t) wdc_get_hdd_cylinder() blocks = (uint32_t)wdc_get_hdd_sectors() * (uint32_t)wdc_get_hdd_heads() * (uint32_t)wdc_get_hdd_cylinder()
- (uint32_t)wdc_get_hdd_sectors() * (uint32_t)wdc_get_hdd_heads(); - (uint32_t)wdc_get_hdd_sectors() * (uint32_t)wdc_get_hdd_heads();
zw0 = blocks / 65536; zw0 = blocks / 65536;
@ -239,30 +248,33 @@ void wdc_set_disk_valid()
par_table[95] = 0x00; par_table[95] = 0x00;
} }
void wdc_set_no_disk() void wdc_set_no_disk ()
{ {
uint8_t i; uint8_t i;
valid_disk = 0; valid_disk = 0;
for ( i = 0; i < 128; i++ )
for ( i = 0; i < 128; i++ ) {
par_table[i] = par_tab_no_dsk[i]; par_table[i] = par_tab_no_dsk[i];
}
} }
uint8_t wdc_get_disk_valid() uint8_t wdc_get_disk_valid ()
{ {
return valid_disk; return valid_disk;
} }
uint8_t wdc_get_num_of_drvs() uint8_t wdc_get_num_of_drvs ()
{ {
return par_table[49]; return par_table[49];
} }
void wdc_set_initialized(uint8_t num) void wdc_set_initialized ( uint8_t num )
{ {
initialized=num; initialized = num;
} }
uint8_t wdc_get_initialized() uint8_t wdc_get_initialized ()
{ {
return initialized; return initialized;
} }

32
P8000_WDC_Emulator/P8000_WDC_Emulator/wdc_par.h
View File

@ -26,7 +26,7 @@
*/ */
/* /*
* $Id: wdc_par.h,v 1.5 2013/04/20 23:22:47 olivleh1 Exp $ * $Id: wdc_par.h,v 1.6 2013/05/04 15:40:15 olivleh1 Exp $
*/ */
#ifndef WDC_PAR_H_ #ifndef WDC_PAR_H_
@ -38,27 +38,27 @@ extern void wdc_write_par_table ( uint8_t *buffer, uint16_t count );
extern void wdc_read_wdc_par ( uint8_t *buffer, uint16_t count ); extern void wdc_read_wdc_par ( uint8_t *buffer, uint16_t count );
extern void wdc_write_wdc_par ( uint8_t *buffer, uint16_t count ); extern void wdc_write_wdc_par ( uint8_t *buffer, uint16_t count );
extern void wdc_del_wdc_btt(); extern void wdc_del_wdc_btt ();
extern void wdc_read_wdc_btt ( uint8_t *buffer, uint16_t count ); extern void wdc_read_wdc_btt ( uint8_t *buffer, uint16_t count );
extern void wdc_write_wdc_btt ( uint8_t *buffer, uint16_t count ); extern void wdc_write_wdc_btt ( uint8_t *buffer, uint16_t count );
extern uint16_t wdc_get_btt_count(); extern uint16_t wdc_get_btt_count ();
extern uint8_t wdc_add_btt_entry ( uint16_t cylinder, uint8_t head ); extern uint8_t wdc_add_btt_entry ( uint16_t cylinder, uint8_t head );
extern uint8_t wdc_get_hdd_sectors(); extern uint8_t wdc_get_hdd_sectors ();
extern uint8_t wdc_get_hdd_heads(); extern uint8_t wdc_get_hdd_heads ();
extern void wdc_set_disk_invalid(); extern void wdc_set_disk_invalid ();
extern void wdc_set_disk_valid(); extern void wdc_set_disk_valid ();
extern uint8_t wdc_get_disk_valid(); extern uint8_t wdc_get_disk_valid ();
extern void wdc_set_no_disk(); extern void wdc_set_no_disk ();
extern uint8_t wdc_get_num_of_drvs(); extern uint8_t wdc_get_num_of_drvs ();
extern void wdc_set_initialized ( uint8_t num ); extern void wdc_set_initialized ( uint8_t num );
extern uint8_t wdc_get_initialized (); extern uint8_t wdc_get_initialized ();
#define POS_PAR_VERSION 0 #define POS_PAR_VERSION 0 /* defines at which position in the PAR table the WDC version string starts */
#define POS_PAR_WDC_PAR 8 #define POS_PAR_WDC_PAR 8 /* defines at which position in the PAR table the WDC parameter section starts */
#define POS_PAR_WDC_BTT 0x88 #define POS_PAR_WDC_BTT 0x88 /* defines at which position in the PAR table the BTT section starts */
#define SIZE_PAR_VERSION 8 #define SIZE_PAR_VERSION 8 /* defines the length of the WDC version string */
#define SIZE_PAR_WDC_PAR 0x80 #define SIZE_PAR_WDC_PAR 0x80 /* defines the length of the WDC parameter section */
#define SIZE_PAR_WDC_BTT 125 #define SIZE_PAR_WDC_BTT 125 /* defines the length of the BTT section */
#endif /* WDC_PAR_H_ */ #endif /* WDC_PAR_H_ */

2
P8000_WDC_Emulator/P8000_WDC_Emulator/wdc_ram.c
View File

@ -26,7 +26,7 @@
*/ */
/* /*
* $Id: wdc_ram.c,v 1.6 2013/04/20 23:22:47 olivleh1 Exp $ * $Id: wdc_ram.c,v 1.7 2013/05/04 15:40:15 olivleh1 Exp $
*/ */
#include <avr/pgmspace.h> #include <avr/pgmspace.h>

4
P8000_WDC_Emulator/P8000_WDC_Emulator/wdc_ram.h
View File

@ -26,7 +26,7 @@
*/ */
/* /*
* $Id: wdc_ram.h,v 1.6 2013/04/20 23:22:47 olivleh1 Exp $ * $Id: wdc_ram.h,v 1.7 2013/05/04 15:40:15 olivleh1 Exp $
*/ */
#ifndef WDC_RAM_H_ #ifndef WDC_RAM_H_
@ -35,6 +35,6 @@
extern void wdc_write_data_to_ram ( uint8_t *buffer, uint16_t address, uint16_t count ); extern void wdc_write_data_to_ram ( uint8_t *buffer, uint16_t address, uint16_t count );
extern void wdc_read_data_from_ram ( uint8_t *buffer, uint16_t address, uint16_t count ); extern void wdc_read_data_from_ram ( uint8_t *buffer, uint16_t address, uint16_t count );
#define convert_ram_address(x) ((x) - 0x2000) /* The S-RAM of the original WDC hardware starts at 0x2000. We use an array as RAM here and no direct RAM access */ #define convert_ram_address( x ) (( x ) - 0x2000 ) /* The S-RAM of the original WDC hardware starts at 0x2000. We use an array as RAM here and no direct RAM access */
#endif /* WDC_RAM_H_ */ #endif /* WDC_RAM_H_ */