chrissy
/
P8000
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

format the code using uncrustify 

migrate uart.[ch] to a BSD style license by reimplementing it
This commit is contained in:
Oliver Lehmann 2013-05-04 15:40:14 +00:00
parent 71a73da3a3
commit 33fd0a9dc5
17 changed files with 404 additions and 402 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

199
P8000_WDC_Emulator/P8000_WDC_Emulator/uart.c
View File

@ -1,119 +1,83 @@
/* /*-
* Copyright (c) 2006-2011 by Roland Riegel <feedback@roland-riegel.de> * Copyright (c) 2013 Oliver Lehmann
* All rights reserved.
* *
* This file is free software; you can redistribute it and/or modify * Redistribution and use in source and binary forms, with or without
* it under the terms of the GNU General Public License version 2 as * modification, are permitted provided that the following conditions
* published by the Free Software Foundation. * are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer
* in this position and unchanged.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/*
* $Id: uart.c,v 1.6 2013/05/04 15:40:14 olivleh1 Exp $
*/ */
#include <stdio.h> #include <stdio.h>
#include <avr/interrupt.h> #include <avr/interrupt.h>
#include <avr/io.h> #include <avr/io.h>
#include <avr/pgmspace.h>
#include <avr/sfr_defs.h> #include <avr/sfr_defs.h>
#include <avr/sleep.h> #include <avr/sleep.h>
#include "uart.h" #include "uart.h"
#include "wdc_config.h" #include "wdc_config.h"
/* some mcus have multiple uarts */ /* Define baud rate */
#ifdef UDR0
#define UBRRH UBRR0H
#define UBRRL UBRR0L
#define UDR UDR0
#define UCSRA UCSR0A
#define UDRE UDRE0
#define RXC RXC0
#define UCSRB UCSR0B
#define RXEN RXEN0
#define TXEN TXEN0
#define RXCIE RXCIE0
#define UCSRC UCSR0C
#define URSEL
#define UCSZ0 UCSZ00
#define UCSZ1 UCSZ01
#define UCSRC_SELECT 0
#else
#define UCSRC_SELECT (1 << URSEL)
#endif
#ifndef USART_RXC_vect
#if defined(UART0_RX_vect)
#define USART_RXC_vect UART0_RX_vect
#elif defined(UART_RX_vect)
#define USART_RXC_vect UART_RX_vect
#elif defined(USART0_RX_vect)
#define USART_RXC_vect USART0_RX_vect
#elif defined(USART_RX_vect)
#define USART_RXC_vect USART_RX_vect
#elif defined(USART0_RXC_vect)
#define USART_RXC_vect USART0_RXC_vect
#elif defined(USART_RXC_vect)
#define USART_RXC_vect USART_RXC_vect
#else
#error "Uart receive complete interrupt not defined!"
#endif
#endif
#define BAUD 9600UL #define BAUD 9600UL
#define UBRRVAL (F_CPU/(BAUD*16)-1) #define UBBR_VALUE (( F_CPU / ( BAUD * 16 )) - 1 )
#define USE_SLEEP 1
void uart_init () void uart_init ()
{ {
/* set baud rate */ /* Set baud rate */
UBRRH = UBRRVAL >> 8; UBRR0H = (uint8_t)( UBBR_VALUE >> 8 );
UBRRL = UBRRVAL & 0xff; UBRR0L = (uint8_t)UBBR_VALUE;
/* set frame format: 8 bit, no parity, 1 bit */ /* Set frame format to 8 data bits, no parity, 1 stop bit */
UCSRC = UCSRC_SELECT | (1 << UCSZ1) | (1 << UCSZ0); UCSR0C = ( 0 << USBS0 ) | ( 1 << UCSZ01 ) | ( 1 << UCSZ00 );
/* enable serial receiver and transmitter */ /* Enable receiver and transmitter */
#if !USE_SLEEP UCSR0B = ( 1 << RXEN0 ) | ( 1 << TXEN0 );
UCSRB = (1 << RXEN) | (1 << TXEN);
#else
UCSRB = (1 << RXEN) | (1 << TXEN) | (1 << RXCIE);
#endif
} }
void uart_putc(uint8_t c) void uart_putc ( uint8_t data )
{ {
if(c == '\n') /* Wait if a byte is being transmitted */
uart_putc('\r'); while ( ( UCSR0A & ( 1 << UDRE0 ) ) == 0 ) {}
/* wait until transmit buffer is empty */ /* Transmit data */
while(!(UCSRA & (1 << UDRE))); UDR0 = data;
/* send next byte */
UDR = c;
} }
void uart_putc_hex ( uint8_t b ) void uart_putc_hex ( uint8_t b )
{ {
/* upper nibble */ /* upper nibble */
if((b >> 4) < 0x0a) if ( ( b >> 4 ) < 0x0a ) {
uart_putc ( ( b >> 4 ) + '0' ); uart_putc ( ( b >> 4 ) + '0' );
else } else {
uart_putc ( ( b >> 4 ) - 0x0a + 'a' ); uart_putc ( ( b >> 4 ) - 0x0a + 'a' );
}
/* lower nibble */ /* lower nibble */
if((b & 0x0f) < 0x0a) if ( ( b & 0x0f ) < 0x0a ) {
uart_putc ( ( b & 0x0f ) + '0' ); uart_putc ( ( b & 0x0f ) + '0' );
else } else {
uart_putc ( ( b & 0x0f ) - 0x0a + 'a' ); uart_putc ( ( b & 0x0f ) - 0x0a + 'a' );
} }
void uart_putw_hex(uint16_t w)
{
uart_putc_hex((uint8_t) (w >> 8));
uart_putc_hex((uint8_t) (w & 0xff));
}
void uart_putdw_hex(uint32_t dw)
{
uart_putw_hex((uint16_t) (dw >> 16));
uart_putw_hex((uint16_t) (dw & 0xffff));
} }
void uart_putw_dec ( uint16_t w ) void uart_putw_dec ( uint16_t w )
@ -121,16 +85,15 @@ void uart_putw_dec(uint16_t w)
uint16_t num = 10000; uint16_t num = 10000;
uint8_t started = 0; uint8_t started = 0;
while(num > 0) while ( num > 0 ) {
{
uint8_t b = w / num; uint8_t b = w / num;
if(b > 0 || started || num == 1)
{ if ( b > 0 || started || num == 1 ) {
uart_putc ( '0' + b ); uart_putc ( '0' + b );
started = 1; started = 1;
} }
w -= b * num;
w -= b * num;
num /= 10; num /= 10;
} }
} }
@ -140,59 +103,43 @@ void uart_putdw_dec(uint32_t dw)
uint32_t num = 1000000000; uint32_t num = 1000000000;
uint8_t started = 0; uint8_t started = 0;
while(num > 0) while ( num > 0 ) {
{
uint8_t b = dw / num; uint8_t b = dw / num;
if(b > 0 || started || num == 1)
{ if ( b > 0 || started || num == 1 ) {
uart_putc ( '0' + b ); uart_putc ( '0' + b );
started = 1; started = 1;
} }
dw -= b * num;
dw -= b * num;
num /= 10; num /= 10;
} }
} }
void uart_puts(const char* str) void uart_put_nl ()
{ {
while(*str) uart_putc ( '\n' );
uart_putc(*str++); uart_putc ( '\r' );
} }
void uart_puts_p(PGM_P str) void uart_putstring ( PGM_P str, bool newline )
{ {
while(1) uint8_t i = 0;
{
uint8_t b = pgm_read_byte_near(str++); while ( 1 ) {
if(!b) char c = pgm_read_byte ( &str[i] );
if ( c != '\0' ) {
uart_putc ( c );
i++;
} else {
break; break;
uart_putc(b);
} }
} }
uint8_t uart_getc() if ( newline ) {
{ uart_put_nl();
uint8_t b; }
/* wait until receive buffer is full */
#if USE_SLEEP
uint8_t sreg = SREG;
sei();
while(!(UCSRA & (1 << RXC)))
sleep_mode();
SREG = sreg;
#else
while(!(UCSRA & (1 << RXC)));
#endif
b = UDR;
if(b == '\r')
b = '\n';
return b;
} }
EMPTY_INTERRUPT(USART_RXC_vect) EMPTY_INTERRUPT ( USART0_RX_vect )

40
P8000_WDC_Emulator/P8000_WDC_Emulator/uart.h
View File

@ -1,15 +1,39 @@
/* /*-
* Copyright (c) 2006-2011 by Roland Riegel <feedback@roland-riegel.de> * Copyright (c) 2013 Oliver Lehmann
* All rights reserved.
* *
* This file is free software; you can redistribute it and/or modify * Redistribution and use in source and binary forms, with or without
* it under the terms of the GNU General Public License version 2 as * modification, are permitted provided that the following conditions
* published by the Free Software Foundation. * are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer
* in this position and unchanged.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/*
* $Id: uart.h,v 1.2 2013/05/04 15:40:14 olivleh1 Exp $
*/ */
#ifndef UART_H #ifndef UART_H
#define UART_H #define UART_H
#include <stdint.h> #include <stdint.h>
#include <stdbool.h>
#include <avr/pgmspace.h> #include <avr/pgmspace.h>
#ifdef __cplusplus #ifdef __cplusplus
@ -22,16 +46,14 @@ void uart_init();
void uart_putc ( uint8_t c ); void uart_putc ( uint8_t c );
void uart_putc_hex ( uint8_t b ); void uart_putc_hex ( uint8_t b );
void uart_putw_hex(uint16_t w);
void uart_putdw_hex(uint32_t dw);
void uart_putw_dec ( uint16_t w ); void uart_putw_dec ( uint16_t w );
void uart_putdw_dec ( uint32_t dw ); void uart_putdw_dec ( uint32_t dw );
void uart_puts ( const char *str ); void uart_puts ( const char *str );
void uart_puts_p(PGM_P str); void uart_putstring ( PGM_P str, bool newline );
uint8_t uart_getc(); void uart_put_nl ();
#ifdef __cplusplus #ifdef __cplusplus
} }

5
P8000_WDC_Emulator/P8000_WDC_Emulator/wdc_avr.c
View File

@ -26,10 +26,9 @@
*/ */
/* /*
* $Id: wdc_avr.c,v 1.5 2013/04/20 23:22:47 olivleh1 Exp $ * $Id: wdc_avr.c,v 1.6 2013/05/04 15:40:14 olivleh1 Exp $
*/ */
#include <avr/io.h> #include <avr/io.h>
#include "wdc_config.h" #include "wdc_config.h"
#include "wdc_avr.h" #include "wdc_avr.h"
@ -86,6 +85,7 @@ void wdc_get_sysconf()
enable_sysconf(); enable_sysconf();
nop(); nop();
nop(); nop();
if ( jumper_pata_set() ) { if ( jumper_pata_set() ) {
drv_init = pata_init; drv_init = pata_init;
drv_read_block = pata_read_block; drv_read_block = pata_read_block;
@ -99,5 +99,6 @@ void wdc_get_sysconf()
drv_read_multiblock = mmc_read_multiblock; drv_read_multiblock = mmc_read_multiblock;
drv_write_multiblock = mmc_write_multiblock; drv_write_multiblock = mmc_write_multiblock;
} }
disable_sysconf(); disable_sysconf();
} }

3
P8000_WDC_Emulator/P8000_WDC_Emulator/wdc_avr.h
View File

@ -26,10 +26,9 @@
*/ */
/* /*
* $Id: wdc_avr.h,v 1.6 2013/04/21 20:19:41 olivleh1 Exp $ * $Id: wdc_avr.h,v 1.7 2013/05/04 15:40:14 olivleh1 Exp $
*/ */
#ifndef WDC_AVR_H_ #ifndef WDC_AVR_H_
#define WDC_AVR_H_ #define WDC_AVR_H_

3
P8000_WDC_Emulator/P8000_WDC_Emulator/wdc_config.h
View File

@ -26,10 +26,9 @@
*/ */
/* /*
* $Id: wdc_config.h,v 1.21 2013/04/20 23:22:47 olivleh1 Exp $ * $Id: wdc_config.h,v 1.22 2013/05/04 15:40:14 olivleh1 Exp $
*/ */
#ifndef CONFIG_H_ #ifndef CONFIG_H_
#define CONFIG_H_ #define CONFIG_H_

4
P8000_WDC_Emulator/P8000_WDC_Emulator/wdc_drv_mmc.h
View File

@ -26,7 +26,7 @@
*/ */
/* /*
* $Id: wdc_drv_mmc.h,v 1.9 2013/04/20 23:22:47 olivleh1 Exp $ * $Id: wdc_drv_mmc.h,v 1.10 2013/05/04 15:40:14 olivleh1 Exp $
*/ */
#ifndef WDC_DRV_MMC_H_ #ifndef WDC_DRV_MMC_H_
@ -43,5 +43,3 @@ extern uint8_t mmc_write_multiblock ( uint32_t addr, uint8_t *buffer, uint8_t nu
#define MMC_BLOCKLEN 512 #define MMC_BLOCKLEN 512
#endif /* WDC_DRV_MMC_H_ */ #endif /* WDC_DRV_MMC_H_ */

2
P8000_WDC_Emulator/P8000_WDC_Emulator/wdc_drv_pata.h
View File

@ -26,7 +26,7 @@
*/ */
/* /*
* $Id: wdc_drv_pata.h,v 1.8 2013/04/20 23:22:47 olivleh1 Exp $ * $Id: wdc_drv_pata.h,v 1.9 2013/05/04 15:40:14 olivleh1 Exp $
*/ */
#ifndef WDC_DRV_PATA_H_ #ifndef WDC_DRV_PATA_H_

50
P8000_WDC_Emulator/P8000_WDC_Emulator/wdc_if_disk.c
View File

@ -26,7 +26,7 @@
*/ */
/* /*
* $Id: wdc_if_disk.c,v 1.14 2013/04/20 23:22:47 olivleh1 Exp $ * $Id: wdc_if_disk.c,v 1.15 2013/05/04 15:40:14 olivleh1 Exp $
*/ */
#include <stdint.h> #include <stdint.h>
@ -43,15 +43,15 @@ uint8_t wdc_init_disk()
uint32_t wdc_sector2diskblock ( uint16_t req_cylinder, uint8_t req_head, uint8_t req_sector ) uint32_t wdc_sector2diskblock ( uint16_t req_cylinder, uint8_t req_head, uint8_t req_sector )
{ {
return ( ( req_cylinder * wdc_get_hdd_heads() * wdc_get_hdd_sectors() ) return ( req_cylinder * wdc_get_hdd_heads() * wdc_get_hdd_sectors() )
+ ( req_head * wdc_get_hdd_sectors() ) + ( req_head * wdc_get_hdd_sectors() )
+ ( req_sector - 1 ) ); + ( req_sector - 1 );
} }
uint32_t wdc_p8kblock2diskblock ( uint32_t blockno ) uint32_t wdc_p8kblock2diskblock ( uint32_t blockno )
{ {
return ( blockno return blockno
+ ( wdc_get_hdd_heads() * wdc_get_hdd_sectors() ) ); + ( wdc_get_hdd_heads() * wdc_get_hdd_sectors() );
} }
uint8_t wdc_write_sector ( uint32_t addr, uint8_t *sector ) uint8_t wdc_write_sector ( uint32_t addr, uint8_t *sector )
@ -59,61 +59,69 @@ uint8_t wdc_write_sector ( uint32_t addr, uint8_t *sector )
uint8_t errorcode; uint8_t errorcode;
errorcode = drv_write_block ( addr, sector ); errorcode = drv_write_block ( addr, sector );
if ( errorcode ) { if ( errorcode ) {
uart_puts_p ( PSTR ( " write error at address: " ) ); uart_putstring ( PSTR ( "ERROR: write error at address: " ), false );
uart_putdw_dec ( addr ); uart_putdw_dec ( addr );
uart_puts_p ( PSTR ( " / errorcode is: " ) ); uart_putstring ( PSTR ( " / errorcode is: " ), false );
uart_putc_hex ( errorcode ); uart_putc_hex ( errorcode );
uart_putc ( '\n' ); uart_put_nl();
return errorcode; return errorcode;
} else } else {
return 0; return 0;
} }
}
uint8_t wdc_read_sector ( uint32_t addr, uint8_t *sector ) uint8_t wdc_read_sector ( uint32_t addr, uint8_t *sector )
{ {
uint8_t errorcode; uint8_t errorcode;
errorcode = drv_read_block ( addr, sector ); errorcode = drv_read_block ( addr, sector );
if ( errorcode ) { if ( errorcode ) {
uart_puts_p ( PSTR ( " read error at address: " ) ); uart_putstring ( PSTR ( "ERROR: read error at address: " ), false );
uart_putdw_dec ( addr ); uart_putdw_dec ( addr );
uart_puts_p ( PSTR ( " / errorcode is: " ) ); uart_putstring ( PSTR ( " / errorcode is: " ), false );
uart_putc_hex ( errorcode ); uart_putc_hex ( errorcode );
uart_putc ( '\n' ); uart_put_nl();
return errorcode; return errorcode;
} else } else {
return 0; return 0;
} }
}
uint8_t wdc_read_multiblock ( uint32_t addr, uint8_t *sector, uint8_t numblocks ) uint8_t wdc_read_multiblock ( uint32_t addr, uint8_t *sector, uint8_t numblocks )
{ {
uint8_t errorcode; uint8_t errorcode;
errorcode = drv_read_multiblock ( addr, sector, numblocks ); errorcode = drv_read_multiblock ( addr, sector, numblocks );
if ( errorcode ) { if ( errorcode ) {
uart_puts_p ( PSTR ( " read error at address: " ) ); uart_putstring ( PSTR ( "ERROR: read error at address: " ), false );
uart_putdw_dec ( addr ); uart_putdw_dec ( addr );
uart_puts_p ( PSTR ( " / errorcode is: " ) ); uart_putstring ( PSTR ( " / errorcode is: " ), false );
uart_putc_hex ( errorcode ); uart_putc_hex ( errorcode );
uart_putc ( '\n' ); uart_put_nl();
return errorcode; return errorcode;
} else } else {
return 0; return 0;
} }
}
uint8_t wdc_write_multiblock ( uint32_t addr, uint8_t *sector, uint8_t numblocks ) uint8_t wdc_write_multiblock ( uint32_t addr, uint8_t *sector, uint8_t numblocks )
{ {
uint8_t errorcode; uint8_t errorcode;
errorcode = drv_write_multiblock ( addr, sector, numblocks ); errorcode = drv_write_multiblock ( addr, sector, numblocks );
if ( errorcode ) { if ( errorcode ) {
uart_puts_p ( PSTR ( " write error at address: " ) ); uart_putstring ( PSTR ( "ERROR: write error at address: " ), false );
uart_putdw_dec ( addr ); uart_putdw_dec ( addr );
uart_puts_p ( PSTR ( " / errorcode is: " ) ); uart_putstring ( PSTR ( " / errorcode is: " ), false );
uart_putc_hex ( errorcode ); uart_putc_hex ( errorcode );
uart_putc ( '\n' ); uart_put_nl();
return errorcode; return errorcode;
} else } else {
return 0; return 0;
} }
}

2
P8000_WDC_Emulator/P8000_WDC_Emulator/wdc_if_disk.h
View File

@ -26,7 +26,7 @@
*/ */
/* /*
* $Id: wdc_if_disk.h,v 1.9 2013/04/20 23:22:47 olivleh1 Exp $ * $Id: wdc_if_disk.h,v 1.10 2013/05/04 15:40:14 olivleh1 Exp $
*/ */
#ifndef WDC_IF_DISK_H_ #ifndef WDC_IF_DISK_H_

58
P8000_WDC_Emulator/P8000_WDC_Emulator/wdc_if_disk_perf.c
View File

@ -26,7 +26,7 @@
*/ */
/* /*
* $Id: wdc_if_disk_perf.c,v 1.11 2013/04/20 23:22:47 olivleh1 Exp $ * $Id: wdc_if_disk_perf.c,v 1.12 2013/05/04 15:40:15 olivleh1 Exp $
*/ */
#include <avr/io.h> #include <avr/io.h>
@ -45,8 +45,7 @@
#define BLOCKNO 300000 #define BLOCKNO 300000
volatile uint32_t overflow = 0; volatile uint32_t overflow = 0;
ISR ( TIMER0_OVF_vect ) ISR ( TIMER0_OVF_vect ) {
{
overflow++; overflow++;
} }
@ -61,23 +60,28 @@ void test_write4k ( uint8_t numblocks, uint8_t nr_of_tests )
uint32_t blockno = 0; uint32_t blockno = 0;
uint8_t i8, errorcode; uint8_t i8, errorcode;
uart_puts_p ( PSTR ( "Test Write 5000 512B-Blocks with Multiblock-Write (4KB Blocksize):" ) ); uart_putstring ( PSTR ( "Test Write 5000 512B-Blocks with Multiblock-Write (4KB Blocksize):" ) );
uart_putc ( '\n' ); uart_putc ( '\n' );
memset ( &data_buffer[0], 0xCC, WDC_BLOCKLEN * numblocks ); memset ( &data_buffer[0], 0xCC, WDC_BLOCKLEN * numblocks );
for ( i8 = 0; i8 < nr_of_tests; i8++ ) { for ( i8 = 0; i8 < nr_of_tests; i8++ ) {
blockno = BLOCKNO; blockno = BLOCKNO;
for ( starttime = overflow; blockno < ( (uint32_t)BLOCKNO + 5000 ); blockno += numblocks ) { for ( starttime = overflow; blockno < ( (uint32_t)BLOCKNO + 5000 ); blockno += numblocks ) {
errorcode = wdc_write_multiblock ( blockno, data_buffer, numblocks ); errorcode = wdc_write_multiblock ( blockno, data_buffer, numblocks );
if ( errorcode ) { if ( errorcode ) {
break; break;
} }
} }
if ( errorcode )
if ( errorcode ) {
break; break;
}
uart_putdw_dec ( overflow - starttime ); uart_putdw_dec ( overflow - starttime );
uart_putc ( '\n' ); uart_putc ( '\n' );
} }
} }
void test_read4k ( uint8_t numblocks, uint8_t nr_of_tests ) void test_read4k ( uint8_t numblocks, uint8_t nr_of_tests )
@ -86,23 +90,27 @@ void test_read4k ( uint8_t numblocks, uint8_t nr_of_tests )
uint32_t blockno = 0; uint32_t blockno = 0;
uint8_t i8, errorcode; uint8_t i8, errorcode;
uart_puts_p ( PSTR ( "Test Read 5000 512B-Blocks with Multiblock-Read (4KB Blocksize):" ) ); uart_putstring ( PSTR ( "Test Read 5000 512B-Blocks with Multiblock-Read (4KB Blocksize):" ) );
uart_putc ( '\n' ); uart_putc ( '\n' );
for ( i8 = 0; i8 < nr_of_tests; i8++ ) { for ( i8 = 0; i8 < nr_of_tests; i8++ ) {
blockno = BLOCKNO; blockno = BLOCKNO;
for ( starttime = overflow; blockno < ( (uint32_t)BLOCKNO + 5000 ); blockno += numblocks ) { for ( starttime = overflow; blockno < ( (uint32_t)BLOCKNO + 5000 ); blockno += numblocks ) {
errorcode = wdc_read_multiblock ( blockno, data_buffer, numblocks ); errorcode = wdc_read_multiblock ( blockno, data_buffer, numblocks );
if ( errorcode ) { if ( errorcode ) {
break; break;
} }
} }
if ( errorcode )
if ( errorcode ) {
break; break;
}
uart_putdw_dec ( overflow - starttime ); uart_putdw_dec ( overflow - starttime );
uart_putc ( '\n' ); uart_putc ( '\n' );
} }
} }
void test_write512 ( uint8_t numblocks, uint8_t nr_of_tests ) void test_write512 ( uint8_t numblocks, uint8_t nr_of_tests )
@ -111,23 +119,28 @@ void test_write512 ( uint8_t numblocks, uint8_t nr_of_tests )
uint32_t blockno = 0; uint32_t blockno = 0;
uint8_t i8, errorcode; uint8_t i8, errorcode;
uart_puts_p ( PSTR ( "Test Write 5000 512B-Blocks with Singleblock-Write (512B Blocksize):" ) ); uart_putstring ( PSTR ( "Test Write 5000 512B-Blocks with Singleblock-Write (512B Blocksize):" ) );
uart_putc ( '\n' ); uart_putc ( '\n' );
memset ( &data_buffer[0], 0xEF, WDC_BLOCKLEN * numblocks ); memset ( &data_buffer[0], 0xEF, WDC_BLOCKLEN * numblocks );
for ( i8 = 0; i8 < nr_of_tests; i8++ ) { for ( i8 = 0; i8 < nr_of_tests; i8++ ) {
blockno = BLOCKNO; blockno = BLOCKNO;
for ( starttime = overflow; blockno < ( (uint32_t)BLOCKNO + 5000 ); blockno++ ) { for ( starttime = overflow; blockno < ( (uint32_t)BLOCKNO + 5000 ); blockno++ ) {
errorcode = wdc_write_sector ( blockno, data_buffer ); errorcode = wdc_write_sector ( blockno, data_buffer );
if ( errorcode ) { if ( errorcode ) {
break; break;
} }
} }
if ( errorcode )
if ( errorcode ) {
break; break;
}
uart_putdw_dec ( overflow - starttime ); uart_putdw_dec ( overflow - starttime );
uart_putc ( '\n' ); uart_putc ( '\n' );
} }
} }
void test_read512 ( uint8_t numblocks, uint8_t nr_of_tests ) void test_read512 ( uint8_t numblocks, uint8_t nr_of_tests )
@ -136,23 +149,27 @@ void test_read512 ( uint8_t numblocks, uint8_t nr_of_tests )
uint32_t blockno = 0; uint32_t blockno = 0;
uint8_t i8, errorcode; uint8_t i8, errorcode;
uart_puts_p ( PSTR ( "Test Read 5000 512B-Blocks with Singleblock-Read (512B Blocksize):" ) ); uart_putstring ( PSTR ( "Test Read 5000 512B-Blocks with Singleblock-Read (512B Blocksize):" ) );
uart_putc ( '\n' ); uart_putc ( '\n' );
for ( i8 = 0; i8 < nr_of_tests; i8++ ) { for ( i8 = 0; i8 < nr_of_tests; i8++ ) {
blockno = BLOCKNO; blockno = BLOCKNO;
for ( starttime = overflow; blockno < ( (uint32_t)BLOCKNO + 5000 ); blockno++ ) { for ( starttime = overflow; blockno < ( (uint32_t)BLOCKNO + 5000 ); blockno++ ) {
errorcode = wdc_read_sector ( blockno, data_buffer ); errorcode = wdc_read_sector ( blockno, data_buffer );
if ( errorcode ) { if ( errorcode ) {
break; break;
} }
} }
if ( errorcode )
if ( errorcode ) {
break; break;
}
uart_putdw_dec ( overflow - starttime ); uart_putdw_dec ( overflow - starttime );
uart_putc ( '\n' ); uart_putc ( '\n' );
} }
} }
void measure_performance () void measure_performance ()
@ -164,12 +181,10 @@ void measure_performance()
TIMSK0 |= ( 0x01 << TOIE0 ); TIMSK0 |= ( 0x01 << TOIE0 );
TCCR0B = ( 1 << CS01 ); /* Prescaler 8 */ TCCR0B = ( 1 << CS01 ); /* Prescaler 8 */
TCNT0 = 0x00; TCNT0 = 0x00;
uart_putstring ( PSTR ( "Performance Measurement. Displayed are the Timer-Overflows." ) );
uart_puts_p ( PSTR ( "Performance Measurement. Displayed are the Timer-Overflows." ) );
uart_putc ( '\n' ); uart_putc ( '\n' );
uart_puts_p ( PSTR ( "Timer is initialized with a Prescaler 8" ) ); uart_putstring ( PSTR ( "Timer is initialized with a Prescaler 8" ) );
uart_putc ( '\n' ); uart_putc ( '\n' );
test_write512 ( numblocks, nr_of_tests ); test_write512 ( numblocks, nr_of_tests );
test_read512 ( numblocks, nr_of_tests ); test_read512 ( numblocks, nr_of_tests );
test_write512 ( numblocks, nr_of_tests ); test_write512 ( numblocks, nr_of_tests );
@ -183,11 +198,10 @@ void measure_performance()
test_read512 ( numblocks, nr_of_tests ); test_read512 ( numblocks, nr_of_tests );
test_write4k ( numblocks, nr_of_tests ); test_write4k ( numblocks, nr_of_tests );
test_write512 ( numblocks, nr_of_tests ); test_write512 ( numblocks, nr_of_tests );
uart_putstring ( PSTR ( "End" ) );
uart_puts_p ( PSTR ( "End" ) );
uart_putc ( '\n' ); uart_putc ( '\n' );
while ( 1 ); while ( 1 ) {}
} }
#endif #endif

31
P8000_WDC_Emulator/P8000_WDC_Emulator/wdc_if_p8000.c
View File

@ -26,7 +26,7 @@
*/ */
/* /*
* $Id: wdc_if_p8000.c,v 1.15 2013/04/23 20:08:41 olivleh1 Exp $ * $Id: wdc_if_p8000.c,v 1.16 2013/05/04 15:40:15 olivleh1 Exp $
*/ */
#include "wdc_config.h" #include "wdc_config.h"
@ -43,7 +43,6 @@ void wdc_wait_for_reset()
port_info_set ( INFO_CLEAR ); port_info_set ( INFO_CLEAR );
wdc_set_initialized ( 1 ); wdc_set_initialized ( 1 );
} }
} }
uint8_t wdc_read_data_from_p8k ( uint8_t *buffer, uint16_t count, uint8_t wdc_status ) uint8_t wdc_read_data_from_p8k ( uint8_t *buffer, uint16_t count, uint8_t wdc_status )
@ -55,16 +54,19 @@ uint8_t wdc_read_data_from_p8k ( uint8_t *buffer, uint16_t count, uint8_t wdc_st
configure_port_data_read(); configure_port_data_read();
datacnt = 0; datacnt = 0;
port_info_set ( wdc_status ); port_info_set ( wdc_status );
while ( !isset_info_te() )
if ( isset_info_reset() ) while ( !isset_info_te() ) {
if ( isset_info_reset() ) {
return 0; return 0;
while ( !isset_info_wdardy() ); }
}
while ( !isset_info_wdardy() ) {}
do { do {
enable_p8000com(); /* this also generates /ASTB in the moment /WDARDY gets low with a 7403 */ enable_p8000com(); /* this also generates /ASTB in the moment /WDARDY gets low with a 7403 */
while ( isset_info_wdardy() ); while ( isset_info_wdardy() ) {}
*buffer++ = port_data_get(); *buffer++ = port_data_get();
disable_p8000com(); /* this additionally brings /ASTB to high */ disable_p8000com(); /* this additionally brings /ASTB to high */
while ( !isset_info_wdardy() ); while ( !isset_info_wdardy() ) {}
datacnt++; datacnt++;
} while ( datacnt < count ); } while ( datacnt < count );
port_info_set ( INFO_CLEAR ); port_info_set ( INFO_CLEAR );
@ -79,24 +81,25 @@ void wdc_write_data_to_p8k ( uint8_t *buffer, uint16_t count, uint8_t wdc_status
_delay_us ( DELAY_PIO_US ); _delay_us ( DELAY_PIO_US );
port_info_set ( INFO_TR | wdc_status ); port_info_set ( INFO_TR | wdc_status );
while ( isset_info_te() ); while ( isset_info_te() ) {}
configure_port_data_write(); configure_port_data_write();
while ( !isset_info_wdardy() ); while ( !isset_info_wdardy() ) {}
do { do {
enable_p8000com(); /* this also generates /ASTB in the moment /WDARDY gets low with a 7403 */ enable_p8000com(); /* this also generates /ASTB in the moment /WDARDY gets low with a 7403 */
while ( isset_info_wdardy() ); while ( isset_info_wdardy() ) {}
port_data_set ( *buffer++ ); port_data_set ( *buffer++ );
disable_p8000com(); /* this additionally brings /ASTB to high */ disable_p8000com(); /* this additionally brings /ASTB to high */
while ( !isset_info_wdardy() ); while ( !isset_info_wdardy() ) {}
datacnt++; datacnt++;
} while ( datacnt < count ); } while ( datacnt < count );
while ( isset_info_wdardy() );
while ( isset_info_wdardy() ) {}
enable_p8000com(); enable_p8000com();
nop(); nop();
disable_p8000com(); disable_p8000com();
configure_port_data_read(); configure_port_data_read();
while ( !isset_info_wdardy() ); while ( !isset_info_wdardy() ) {}
port_info_set ( INFO_CLEAR ); port_info_set ( INFO_CLEAR );
} }

2
P8000_WDC_Emulator/P8000_WDC_Emulator/wdc_if_p8000.h
View File

@ -26,7 +26,7 @@
*/ */
/* /*
* $Id: wdc_if_p8000.h,v 1.12 2013/04/20 23:22:47 olivleh1 Exp $ * $Id: wdc_if_p8000.h,v 1.13 2013/05/04 15:40:15 olivleh1 Exp $
*/ */
#ifndef WDC_IF_P8000_H_ #ifndef WDC_IF_P8000_H_

5
P8000_WDC_Emulator/P8000_WDC_Emulator/wdc_main.h
View File

@ -26,10 +26,9 @@
*/ */
/* /*
* $Id: wdc_main.h,v 1.13 2013/04/20 23:22:47 olivleh1 Exp $ * $Id: wdc_main.h,v 1.14 2013/05/04 15:40:15 olivleh1 Exp $
*/ */
#ifndef MAIN_H_ #ifndef MAIN_H_
#define MAIN_H_ #define MAIN_H_
@ -57,7 +56,7 @@
#define ___CMD_WRRDBTT_SECTOR 0x92 /* write and reread sector taking BTT into account */ #define ___CMD_WRRDBTT_SECTOR 0x92 /* write and reread sector taking BTT into account */
#define ___CMD_CP_BLOCK 0xa1 /* copy block from drive 1 to drive 0 */ #define ___CMD_CP_BLOCK 0xa1 /* copy block from drive 1 to drive 0 */
#define ___CMD_WRRD_BLOCK 0xa2 /* write and reread block */ #define ___CMD_WRRD_BLOCK 0xa2 /* write and reread block */
#define CMD_ST_PARBTT 0xc2 /* store PAR and BTT on hard disk */ #define CMD_ST_PARBTT 0xc2 /* store Parameter block and BTT on hard disk */
#define ERR_STANDARD 0x01 #define ERR_STANDARD 0x01
#define ERR_SECT_N_ON_SURFACE 0x0A #define ERR_SECT_N_ON_SURFACE 0x0A

38
P8000_WDC_Emulator/P8000_WDC_Emulator/wdc_par.c
View File

@ -26,7 +26,7 @@
*/ */
/* /*
* $Id: wdc_par.c,v 1.8 2013/04/21 00:40:52 olivleh1 Exp $ * $Id: wdc_par.c,v 1.9 2013/05/04 15:40:15 olivleh1 Exp $
*/ */
#include <avr/pgmspace.h> #include <avr/pgmspace.h>
@ -75,7 +75,9 @@
uint8_t par_table[512]; uint8_t par_table[512];
const uint8_t const uint8_t
par_tab_new_dsk[128] = {'W', 'D', 'C', '_', '4', '.', '2', 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, par_tab_new_dsk[128] =
{
'W', 'D', 'C', '_', '4', '.', '2', 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81,
0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x64, 0x00, 0x02, 0x12, 0x64, 0x00, 0x01, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x64, 0x00, 0x02, 0x12, 0x64, 0x00, 0x01, 0x81, 0x81,
0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, /* init with sa.format ends here */ 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, /* init with sa.format ends here */
/* to be initiated by controller starts here */ 0xEB, 0x0D, 0x00, 0x00, 0x41, 0x00, /* to be initiated by controller starts here */ 0xEB, 0x0D, 0x00, 0x00, 0x41, 0x00,
@ -87,7 +89,9 @@ par_tab_new_dsk[128] = {'W', 'D', 'C', '_', '4', '.', '2', 0x81, 0x81, 0x
}; };
const uint8_t const uint8_t
par_tab_no_dsk[128] = {'W', 'D', 'C', '_', '4', '.', '2', 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, par_tab_no_dsk[128] =
{
'W', 'D', 'C', '_', '4', '.', '2', 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81,
0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x64, 0x00, 0x02, 0x12, 0x64, 0x00, 0x01, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x64, 0x00, 0x02, 0x12, 0x64, 0x00, 0x01, 0x81, 0x81,
0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, /* init with sa.format ends here */ 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, /* init with sa.format ends here */
/* to be initiated by controller starts here */ 0x81, 0x81, 0x81, 0x81, 0x40, 0x00, /* to be initiated by controller starts here */ 0x81, 0x81, 0x81, 0x81, 0x40, 0x00,
@ -117,7 +121,6 @@ void wdc_write_par_table ( uint8_t *buffer, uint16_t count )
} while ( count > 0 ); } while ( count > 0 );
} }
void wdc_read_wdc_par ( uint8_t *buffer, uint16_t count ) void wdc_read_wdc_par ( uint8_t *buffer, uint16_t count )
{ {
do { do {
@ -137,8 +140,11 @@ void wdc_write_wdc_par ( uint8_t *buffer, uint16_t count )
void wdc_del_wdc_btt () void wdc_del_wdc_btt ()
{ {
uint8_t i; uint8_t i;
for ( i = 0; i < 125; i++ )
for ( i = 0; i < 125; i++ ) {
par_table[i + POS_PAR_WDC_BTT] = 0x00; par_table[i + POS_PAR_WDC_BTT] = 0x00;
}
par_table[122 + POS_PAR_WDC_BTT] = 0xff; par_table[122 + POS_PAR_WDC_BTT] = 0xff;
} }
@ -160,7 +166,7 @@ void wdc_write_wdc_btt ( uint8_t *buffer, uint16_t count )
uint16_t wdc_get_btt_count () uint16_t wdc_get_btt_count ()
{ {
return ( ( par_table[0 + POS_PAR_WDC_BTT] | ( par_table[1 + POS_PAR_WDC_BTT] << 8 ) ) ); return par_table[0 + POS_PAR_WDC_BTT] | ( par_table[1 + POS_PAR_WDC_BTT] << 8 );
} }
void wdc_set_btt_count ( uint16_t btt_count ) void wdc_set_btt_count ( uint16_t btt_count )
@ -183,24 +189,25 @@ uint8_t wdc_add_btt_entry ( uint16_t cylinder, uint8_t head )
par_table[btt_count + 2 + POS_PAR_WDC_BTT] = (uint8_t)head; par_table[btt_count + 2 + POS_PAR_WDC_BTT] = (uint8_t)head;
btt_count++; btt_count++;
wdc_set_btt_count ( btt_count ); wdc_set_btt_count ( btt_count );
return ( 0 ); return 0;
}else { }else {
return ( ERR_BTT_FULL ); return ERR_BTT_FULL;
} }
} }
uint8_t wdc_get_hdd_sectors () uint8_t wdc_get_hdd_sectors ()
{ {
return ( par_table[18 + POS_PAR_WDC_PAR] ); return par_table[18 + POS_PAR_WDC_PAR];
} }
uint8_t wdc_get_hdd_heads () uint8_t wdc_get_hdd_heads ()
{ {
return ( par_table[17 + POS_PAR_WDC_PAR] ); return par_table[17 + POS_PAR_WDC_PAR];
} }
uint16_t wdc_get_hdd_cylinder () uint16_t wdc_get_hdd_cylinder ()
{ {
return ( ( par_table[16 + POS_PAR_WDC_PAR] << 8 ) | par_table[15 + POS_PAR_WDC_PAR] ); return ( par_table[16 + POS_PAR_WDC_PAR] << 8 ) | par_table[15 + POS_PAR_WDC_PAR];
} }
void wdc_set_disk_invalid () void wdc_set_disk_invalid ()
@ -208,9 +215,11 @@ void wdc_set_disk_invalid()
uint8_t i; uint8_t i;
valid_disk = 0; valid_disk = 0;
for ( i = 0; i < 128; i++ )
for ( i = 0; i < 128; i++ ) {
par_table[i] = par_tab_new_dsk[i]; par_table[i] = par_tab_new_dsk[i];
} }
}
void wdc_set_disk_valid () void wdc_set_disk_valid ()
{ {
@ -242,10 +251,13 @@ void wdc_set_disk_valid()
void wdc_set_no_disk () void wdc_set_no_disk ()
{ {
uint8_t i; uint8_t i;
valid_disk = 0; valid_disk = 0;
for ( i = 0; i < 128; i++ )
for ( i = 0; i < 128; i++ ) {
par_table[i] = par_tab_no_dsk[i]; par_table[i] = par_tab_no_dsk[i];
} }
}
uint8_t wdc_get_disk_valid () uint8_t wdc_get_disk_valid ()
{ {

14
P8000_WDC_Emulator/P8000_WDC_Emulator/wdc_par.h
View File

@ -26,7 +26,7 @@
*/ */
/* /*
* $Id: wdc_par.h,v 1.5 2013/04/20 23:22:47 olivleh1 Exp $ * $Id: wdc_par.h,v 1.6 2013/05/04 15:40:15 olivleh1 Exp $
*/ */
#ifndef WDC_PAR_H_ #ifndef WDC_PAR_H_
@ -53,12 +53,12 @@ extern uint8_t wdc_get_num_of_drvs();
extern void wdc_set_initialized ( uint8_t num ); extern void wdc_set_initialized ( uint8_t num );
extern uint8_t wdc_get_initialized (); extern uint8_t wdc_get_initialized ();
#define POS_PAR_VERSION 0 #define POS_PAR_VERSION 0 /* defines at which position in the PAR table the WDC version string starts */
#define POS_PAR_WDC_PAR 8 #define POS_PAR_WDC_PAR 8 /* defines at which position in the PAR table the WDC parameter section starts */
#define POS_PAR_WDC_BTT 0x88 #define POS_PAR_WDC_BTT 0x88 /* defines at which position in the PAR table the BTT section starts */
#define SIZE_PAR_VERSION 8 #define SIZE_PAR_VERSION 8 /* defines the length of the WDC version string */
#define SIZE_PAR_WDC_PAR 0x80 #define SIZE_PAR_WDC_PAR 0x80 /* defines the length of the WDC parameter section */
#define SIZE_PAR_WDC_BTT 125 #define SIZE_PAR_WDC_BTT 125 /* defines the length of the BTT section */
#endif /* WDC_PAR_H_ */ #endif /* WDC_PAR_H_ */

2
P8000_WDC_Emulator/P8000_WDC_Emulator/wdc_ram.c
View File

@ -26,7 +26,7 @@
*/ */
/* /*
* $Id: wdc_ram.c,v 1.6 2013/04/20 23:22:47 olivleh1 Exp $ * $Id: wdc_ram.c,v 1.7 2013/05/04 15:40:15 olivleh1 Exp $
*/ */
#include <avr/pgmspace.h> #include <avr/pgmspace.h>

2
P8000_WDC_Emulator/P8000_WDC_Emulator/wdc_ram.h
View File

@ -26,7 +26,7 @@
*/ */
/* /*
* $Id: wdc_ram.h,v 1.6 2013/04/20 23:22:47 olivleh1 Exp $ * $Id: wdc_ram.h,v 1.7 2013/05/04 15:40:15 olivleh1 Exp $
*/ */
#ifndef WDC_RAM_H_ #ifndef WDC_RAM_H_